JPWO2020241775A1 - - Google Patents

Info

Publication number
JPWO2020241775A1
JPWO2020241775A1 JP2021522875A JP2021522875A JPWO2020241775A1 JP WO2020241775 A1 JPWO2020241775 A1 JP WO2020241775A1 JP 2021522875 A JP2021522875 A JP 2021522875A JP 2021522875 A JP2021522875 A JP 2021522875A JP WO2020241775 A1 JPWO2020241775 A1 JP WO2020241775A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2021522875A
Other versions
JP7307161B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2020241775A1 publication Critical patent/JPWO2020241775A1/ja
Priority to JP2023107470A priority Critical patent/JP2023126865A/ja
Application granted granted Critical
Publication of JP7307161B2 publication Critical patent/JP7307161B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867Applying pastes or inks, e.g. screen printing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • H05K1/116Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/184Components including terminals inserted in holes through the printed circuit board and connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09454Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2021522875A 2019-05-29 2020-05-28 電子素子実装用基板、電子装置、および電子モジュール Active JP7307161B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023107470A JP2023126865A (ja) 2019-05-29 2023-06-29 電子素子実装用基板、電子装置、および電子モジュール

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019100404 2019-05-29
JP2019100404 2019-05-29
PCT/JP2020/021181 WO2020241775A1 (ja) 2019-05-29 2020-05-28 電子素子実装用基板、電子装置、および電子モジュール

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2023107470A Division JP2023126865A (ja) 2019-05-29 2023-06-29 電子素子実装用基板、電子装置、および電子モジュール

Publications (2)

Publication Number Publication Date
JPWO2020241775A1 true JPWO2020241775A1 (ja) 2020-12-03
JP7307161B2 JP7307161B2 (ja) 2023-07-11

Family

ID=73552185

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2021522875A Active JP7307161B2 (ja) 2019-05-29 2020-05-28 電子素子実装用基板、電子装置、および電子モジュール
JP2023107470A Pending JP2023126865A (ja) 2019-05-29 2023-06-29 電子素子実装用基板、電子装置、および電子モジュール

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2023107470A Pending JP2023126865A (ja) 2019-05-29 2023-06-29 電子素子実装用基板、電子装置、および電子モジュール

Country Status (4)

Country Link
US (1) US20220361333A1 (ja)
JP (2) JP7307161B2 (ja)
CN (1) CN113875000A (ja)
WO (1) WO2020241775A1 (ja)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273455A (ja) * 1994-03-30 1995-10-20 Oki Electric Ind Co Ltd 多層セラミック基板及びその製造方法
WO2002074029A1 (en) * 2001-03-14 2002-09-19 Ibiden Co., Ltd. Multilayer printed wiring board
JP2004111769A (ja) * 2002-09-20 2004-04-08 Kyocera Corp 電子部品搭載用基板
JP2005072503A (ja) * 2003-08-27 2005-03-17 Kyocera Corp 配線基板およびそれを用いた電子装置
JP2006269692A (ja) * 2005-03-23 2006-10-05 Tdk Corp 多層セラミック基板及びその製造方法
JP2017050391A (ja) * 2015-09-01 2017-03-09 株式会社デンソー 多層基板およびその製造方法
JP2019079987A (ja) * 2017-10-26 2019-05-23 京セラ株式会社 電子素子実装用基板、電子装置および電子モジュール

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140621B1 (ja) * 1971-02-10 1976-11-05
JPS5122060A (ja) * 1974-08-19 1976-02-21 Fujitsu Ltd Tasopurintoban
JPH0717166Y2 (ja) * 1988-06-28 1995-04-19 株式会社フジクラ 多層フレキシブルプリント配線板
JP2005150552A (ja) * 2003-11-18 2005-06-09 Ngk Spark Plug Co Ltd 配線基板の製造方法
WO2008108172A1 (ja) * 2007-03-01 2008-09-12 Murata Manufacturing Co., Ltd. 多層配線基板
JP5574038B2 (ja) * 2011-03-07 2014-08-20 株式会社村田製作所 セラミック多層基板およびその製造方法
JP5835282B2 (ja) * 2013-07-04 2015-12-24 株式会社村田製作所 多層配線基板の製造方法およびプローブカードの製造方法並びに多層配線基板およびプローブカード
JP2017123377A (ja) * 2016-01-05 2017-07-13 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
JP6832630B2 (ja) * 2016-03-28 2021-02-24 富士通インターコネクトテクノロジーズ株式会社 配線基板の製造方法
TW202339757A (zh) 2022-01-19 2023-10-16 日商塩野義製藥股份有限公司 新型冠狀病毒感染症治療用醫藥

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273455A (ja) * 1994-03-30 1995-10-20 Oki Electric Ind Co Ltd 多層セラミック基板及びその製造方法
WO2002074029A1 (en) * 2001-03-14 2002-09-19 Ibiden Co., Ltd. Multilayer printed wiring board
JP2004111769A (ja) * 2002-09-20 2004-04-08 Kyocera Corp 電子部品搭載用基板
JP2005072503A (ja) * 2003-08-27 2005-03-17 Kyocera Corp 配線基板およびそれを用いた電子装置
JP2006269692A (ja) * 2005-03-23 2006-10-05 Tdk Corp 多層セラミック基板及びその製造方法
JP2017050391A (ja) * 2015-09-01 2017-03-09 株式会社デンソー 多層基板およびその製造方法
JP2019079987A (ja) * 2017-10-26 2019-05-23 京セラ株式会社 電子素子実装用基板、電子装置および電子モジュール

Also Published As

Publication number Publication date
US20220361333A1 (en) 2022-11-10
CN113875000A (zh) 2021-12-31
WO2020241775A1 (ja) 2020-12-03
JP7307161B2 (ja) 2023-07-11
JP2023126865A (ja) 2023-09-12

Similar Documents

Publication Publication Date Title
BR112019017762A2 (ja)
BR112021013854A2 (ja)
BR112021018450A2 (ja)
BR112021017939A2 (ja)
BR112021017738A2 (ja)
BR112021017892A2 (ja)
BR112019016141A2 (ja)
BR112021017782A2 (ja)
AU2020104490A5 (ja)
BR112021008711A2 (ja)
BR112019016138A2 (ja)
BR112019016142A2 (ja)
BR112021018168A2 (ja)
BR112021018452A2 (ja)
BR112021018102A2 (ja)
BR112021018584A2 (ja)
BR112021015080A2 (ja)
BR112021012348A2 (ja)
BR112021018250A2 (ja)
BR112021018093A2 (ja)
BR112021018084A2 (ja)
BR112021013944A2 (ja)
BR112021013128A2 (ja)
BR112021018484A2 (ja)
BR112021017949A2 (ja)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20211119

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20221004

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20221205

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230203

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230530

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230629

R150 Certificate of patent or registration of utility model

Ref document number: 7307161

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150