JPWO2019077438A1 - 半導体装置、および半導体装置の作製方法 - Google Patents
半導体装置、および半導体装置の作製方法 Download PDFInfo
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- JPWO2019077438A1 JPWO2019077438A1 JP2019548786A JP2019548786A JPWO2019077438A1 JP WO2019077438 A1 JPWO2019077438 A1 JP WO2019077438A1 JP 2019548786 A JP2019548786 A JP 2019548786A JP 2019548786 A JP2019548786 A JP 2019548786A JP WO2019077438 A1 JPWO2019077438 A1 JP WO2019077438A1
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Abstract
Description
以下では、本発明の一態様に係るトランジスタ200を有する半導体装置の一例について説明する。
図1は、本発明の一態様に係るトランジスタ200、およびトランジスタ200周辺の上面図および断面図である。
図1に示すように、トランジスタ200は、基板(図示せず)の上に配置された絶縁体214および絶縁体216と、絶縁体214および絶縁体216に埋め込まれるように配置された導電体205(導電体205aおよび導電体205b)と、絶縁体216の上および導電体205の上に配置された絶縁体220と、絶縁体220の上に配置された絶縁体222と、絶縁体222の上に配置された絶縁体224と、絶縁体224の上に配置された酸化物230(酸化物230a、酸化物230b、および酸化物230c)と、酸化物230の上に配置された絶縁体250と、絶縁体250上に配置された導電体260(導電体260a、および導電体260b)と、酸化物230の上面の一部と接する導電体242aおよび導電体242bと、絶縁体224の上面の一部、絶縁体222の上面の一部、酸化物230aの側面、酸化物230bの側面、導電体242aの側面、導電体242aの上面、導電体242bの側面、導電体242bの上面、酸化物230cの側面に接して配置された絶縁体273と、絶縁体273に接して配置された絶縁体274と、を有する。導電体260は、導電体260aおよび導電体260bを有し、導電体260bの底面および側面を包むように導電体260aが配置される。ここで、図1(B)に示すように、導電体260の上面は、絶縁体273の上面および絶縁体274の上面と略一致して配置される。
以下では、半導体装置に用いることができる基板および金属酸化物について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばSOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
酸化物230として、酸化物半導体として機能する金属酸化物(以下、酸化物半導体ともいう)を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
酸化物半導体(金属酸化物)は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC−OS(c−axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc−OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)および非晶質酸化物半導体などがある。
次に、図1に示す、本発明に係るトランジスタ200を有する半導体装置について、作製方法を図4乃至図9を用いて説明する。また、図4乃至図9において、各図の(A)は上面図を示す。また、各図の(B)は、(A)に示すA1−A2の一点鎖線で示す部位に対応する断面図であり、トランジスタ200のチャネル長方向の断面図でもある。また、各図の(C)は、(A)にA3−A4の一点鎖線で示す部位に対応する断面図であり、トランジスタ200のチャネル幅方向の断面図でもある。なお、各図の(A)の上面図では、図の明瞭化のために一部の要素を省いている。
以下では、図10および図11を用いて、先の<半導体装置の構成例>で示したものとは異なる、本発明の一態様に係るトランジスタ200を有する半導体装置の一例について説明する。
本実施の形態では、半導体装置の一形態を、図12および図13を用いて説明する。
本発明の一態様である容量素子を使用した、半導体装置(記憶装置)の一例を図12に示す。本発明の一態様の半導体装置は、トランジスタ200はトランジスタ300の上方に設けられ、容量素子100はトランジスタ300、およびトランジスタ200の上方に設けられている。なお、トランジスタ200として、先の実施の形態で説明したトランジスタ200を用いることができる。
トランジスタ300は、基板311上に設けられ、ゲートとして機能する導電体316、ゲート絶縁体として機能する絶縁体315、基板311の一部からなる半導体領域313、およびソース領域またはドレイン領域として機能する低抵抗領域314a、および低抵抗領域314bを有する。トランジスタ300は、pチャネル型、あるいはnチャネル型のいずれでもよい。
容量素子100は、トランジスタ200の上方に設けられる。容量素子100は、第1の電極として機能する導電体110と、第2の電極として機能する導電体120、および誘電体として機能する絶縁体130とを有する。
各構造体の間には、層間膜、配線、およびプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。ここで、プラグまたは配線としての機能を有する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。
なお、トランジスタ200に、酸化物半導体を用いる場合、酸化物半導体の近傍に過剰酸素領域を有する絶縁体が設けることがある。その場合、該過剰酸素領域を有する絶縁体と、該過剰酸素領域を有する絶縁体に設ける導電体との間に、バリア性を有する絶縁体を設けることが好ましい。
本発明の一態様である半導体装置を使用した、記憶装置の一例を図13に示す。図13に示す記憶装置は、図12で示したトランジスタ200、トランジスタ300、および容量素子100を有する半導体装置に加え、トランジスタ400を有している。
トランジスタ400は、トランジスタ200と、同じ層に形成されており、並行して作製することができるトランジスタである。トランジスタ400は、第1のゲートとして機能する導電体460(導電体460a、および導電体460b)と、第2のゲートとして機能する導電体405と、ゲート絶縁層として機能する絶縁体220、絶縁体222、絶縁体224、および絶縁体450と、チャネルが形成される領域を有する酸化物430cと、ソースまたはドレインの一方として機能する導電体442a、酸化物431a、および酸化物431bと、ソースまたはドレインの他方として機能する導電体442b、酸化物432a、および酸化物432bと、導電体440(導電体440a、および導電体440b)と、を有する。
以下では、大面積基板を半導体素子ごとに分断することによって、複数の半導体装置をチップ状で取り出す場合に設けられるダイシングライン(スクライブライン、分断ライン、又は切断ラインと呼ぶ場合がある)について説明する。分断方法としては、例えば、まず、基板に半導体素子を分断するための溝(ダイシングライン)を形成した後、ダイシングラインにおいて切断し、複数の半導体装置に分断(分割)する方法がある。
本実施の形態では、図14および図15を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ場合がある)、および容量素子が適用されている記憶装置(以下、OSメモリ装置と呼ぶ場合がある)について説明する。OSメモリ装置は、少なくとも容量素子と、容量素子の充放電を制御するOSトランジスタを有する記憶装置である。OSトランジスタのオフ電流は極めて小さいので、OSメモリ装置は優れた保持特性をもち、不揮発性メモリとして機能させることができる。
図14(A)にOSメモリ装置の構成の一例を示す。記憶装置1400は、周辺回路1411、およびメモリセルアレイ1470を有する。周辺回路1411は、行回路1420、列回路1430、出力回路1440、コントロールロジック回路1460を有する。
図15(A)乃至(C)に、DRAMのメモリセルの回路構成例を示す。本明細書等において、1OSトランジスタ1容量素子型のメモリセルを用いたDRAMを、DOSRAM(Dynamic Oxide Semiconductor Random Access Memory)と呼ぶ場合がある。図15(A)に示す、メモリセル1471は、トランジスタM1と、容量素子CAと、を有する。なお、トランジスタM1は、ゲート(フロントゲートと呼ぶ場合がある)、及びバックゲートを有する。
図15(D)乃至(G)に、2トランジスタ1容量素子のゲインセル型のメモリセルの回路構成例を示す。図15(D)に示す、メモリセル1474は、トランジスタM2と、トランジスタM3と、容量素子CBと、を有する。なお、トランジスタM2は、フロントゲート(単にゲートと呼ぶ場合がある)、及びバックゲートを有する。本明細書等において、トランジスタM2にOSトランジスタを用いたゲインセル型のメモリセルを有する記憶装置を、NOSRAM(Nonvolatile Oxide Semiconductor RAM)と呼ぶ場合がある。
本実施の形態では、図16を用いて、本発明の半導体装置が実装されたチップ1200の一例を示す。チップ1200には、複数の回路(システム)が実装されている。このように、複数の回路(システム)を一つのチップに集積する技術を、システムオンチップ(System on Chip:SoC)と呼ぶ場合がある。
本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器(例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ(ビデオカメラも含む)、録画再生装置、ナビゲーションシステムなど)の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータや、ノート型のコンピュータや、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード(例えば、SDカード)、USBメモリ、SSD(ソリッド・ステート・ドライブ)等の各種のリムーバブル記憶装置に適用される。図17にリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いられる。
<電子機器>
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図18に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。
Claims (6)
- 第1の絶縁体と、
前記第1の絶縁体上の第2の絶縁体と、
前記第2の絶縁体上の酸化物と、
前記酸化物上の第1の導電体および第2の導電体と、
前記酸化物上の第3の絶縁体と、
前記第3の絶縁体上に位置し、前記酸化物と重なる第3の導電体と、
前記第2の絶縁体、前記酸化物の側面、前記第1の導電体の側面、前記第1の導電体の上面、前記第2の導電体の側面、前記第2の導電体の上面、および前記第3の絶縁体の側面と接する、第4の絶縁体と、
前記第3の絶縁体および前記第3の導電体の上面と接する、第5の絶縁体と、を有し、
前記第4の絶縁体の上面は、前記第5の絶縁体と接する、
ことを特徴とする半導体装置。 - 第1の絶縁体と、
前記第1の絶縁体上の第2の絶縁体と、
前記第2の絶縁体上の酸化物と、
前記酸化物上の第1の導電体および第2の導電体と、
前記酸化物上の第3の絶縁体と、
前記第3の絶縁体上に位置し、前記酸化物と重なる第3の導電体と、
前記第2の絶縁体、前記酸化物の側面、前記第1の導電体の側面、前記第1の導電体の上面、前記第2の導電体の側面、前記第2の導電体の上面、および前記第3の絶縁体の側面と接する、第4の絶縁体と、
前記第3の絶縁体および前記第3の導電体の上面と接する、第5の絶縁体と、を有し、
前記第4の絶縁体の上面は、前記第5の絶縁体と接し、
前記第2の絶縁体は、前記第1の絶縁体を露出する開口を有し、
前記第4の絶縁体は、前記開口を介して前記第1の絶縁体と接する、
ことを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第1の絶縁体、前記第4の絶縁体および第5の絶縁体は、前記第2の絶縁体、前記第3の絶縁体よりも酸素を透過し難い、ことを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第1の絶縁体、前記第4の絶縁体および第5の絶縁体は、前記第2の絶縁体、前記第3の絶縁体よりも水素を透過し難い、ことを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一項において、
前記第1の絶縁体、前記第4の絶縁体および前記第5の絶縁体は、アルミニウム、およびハフニウムの一方または両方を含む酸化物であることを特徴とする半導体装置。 - 基板上に第1の絶縁体を形成し、
前記第1の絶縁体の上に、酸化膜および第1の導電膜を順に成膜し、
前記酸化膜および前記第1の導電膜を加工して、酸化物および導電体層を形成し、
前記酸化物および前記導電体層を覆ってダミーゲート膜を成膜し、
前記ダミーゲート膜を加工して、ダミーゲート層を形成し、
前記第1の絶縁体、前記酸化物、前記導電体層を覆って、第1の絶縁膜を成膜し、
前記第1の絶縁膜の上に第2の絶縁膜を成膜し、
第1のCMP処理を行うことによって、前記ダミーゲート層、前記第1の絶縁膜および前記第2の絶縁膜の一部を、前記ダミーゲート層の一部が露出するまで除去し、
前記導電体層の一部および前記ダミーゲート層をエッチングすることによって、第1の導電体と第2の導電体を形成し、前記酸化物を露出させ、
第3の絶縁膜、第2の導電膜を順に成膜し、
第2のCMP処理を行うことによって、前記の第3の絶縁膜および前記第2の導電膜を前記第2の絶縁膜の一部が露出するまで除去し、第3絶縁体および第3の導電体を形成し、
前記第2の絶縁膜、前記第3の絶縁体および前記第3の導電体を覆って、第4の絶縁膜を成膜すること、を特徴とする半導体装置の作製方法。
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