JP7208891B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP7208891B2 JP7208891B2 JP2019514881A JP2019514881A JP7208891B2 JP 7208891 B2 JP7208891 B2 JP 7208891B2 JP 2019514881 A JP2019514881 A JP 2019514881A JP 2019514881 A JP2019514881 A JP 2019514881A JP 7208891 B2 JP7208891 B2 JP 7208891B2
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Images
Classifications
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Description
以下では、本発明の一態様に係るトランジスタ200を有する半導体装置の一例について説明する。
図1(A)、図1(B)、図1(C)、および図1(D)は、本発明の一態様に係る半導体装置の上面図、および断面図である。
図1、および図2に示すように、トランジスタ200は、基板(図示せず)の上に配置された絶縁体208、および絶縁体208上に配置された絶縁体210の上に、導電体209と、導電体209の周囲に配置された絶縁体212と、導電体209および絶縁体212の上に配置された導電体205と、導電体205の周囲に配置された絶縁体216と、絶縁体216および導電体205の上に配置された絶縁体220と、絶縁体220の上に配置された絶縁体222(絶縁体222a、絶縁体222b、および絶縁体222c)と、絶縁体222の上に配置された絶縁体224と、絶縁体224の上に配置された酸化物230(酸化物230a、酸化物230b、および酸化物230c)と、酸化物230の上に配置された絶縁体250(絶縁体250a、および絶縁体250b)と、絶縁体250の上に配置された導電体260(導電体260a、および導電体260b)と、導電体260上に配置された絶縁体270と、絶縁体270上に配置された絶縁体271と、少なくとも絶縁体250の側面、および導電体260の側面に接するように配置された絶縁体272と、絶縁体272の上面の一部および側面の一部に接するように配置された絶縁体273と、少なくとも酸化物230、絶縁体271、絶縁体272、および絶縁体273を覆うように配置された絶縁体274と、を有する。
図3は、図1に示した半導体装置とは異なる構成を有する半導体装置の上面図、および断面図である。図3に示す半導体装置は、トランジスタ201と同じ層に、トランジスタ201の構造の一部を用いて容量素子100が設けられている。本明細書において、トランジスタと、容量素子と、を有する半導体装置を、セルと称する場合がある。以降、トランジスタ201と、容量素子100と、を有するセル600について説明する。
図3に示すトランジスタ201において、図1に示すトランジスタ200と共通な部分については同一の符号をしるし、説明を省略する場合がある。
図3に示すように、容量素子100は、トランジスタ201と共通の構造を有する構成である。本実施の形態では、トランジスタ201の酸化物230に設けられた領域231bの一部が、容量素子100の電極の一方として機能する容量素子100の例について示す。
本発明の一態様の半導体装置は、トランジスタ201と、容量素子100、層間膜として機能する絶縁体280を有する。また、トランジスタ201および容量素子100と電気的に接続し、プラグとして機能する導電体252(導電体252a、導電体252b、導電体252c、および導電体252d)とを有する。
成膜装置1000は、搬入搬出室1002と、搬入搬出室1004と、搬送室1006と、成膜室1008と、成膜室1009と、成膜室1010と、搬送アーム1014と、を有する。ここで、搬入搬出室1002、搬入搬出室1004、成膜室1008乃至1010は、搬送室1006と接続されている。これにより、成膜室1008乃至1010において大気に曝すことなく、連続成膜を行うことができ、膜中に不純物が混入するのを防ぐことができる。また、基板と膜の界面、および各膜の界面の汚染は低減され、清浄な界面が得られる。
次に、成膜装置1000に用いることができるALD装置の構成について説明する。ALD装置は、成膜室(チャンバー1020)と、原料供給部1021a、1021b、および1021cと、流量制御器である高速バルブ1022a、1022bと、原料導入口1023a、1023b、および1023cと、原料排出口1024と、排気装置1025を有する。チャンバー1020内に設置される原料導入口1023a、1023b、および1023cは供給管やバルブを介して原料供給部1021a、1021b、および1021cとそれぞれ接続されており、原料排出口1024は、排出管やバルブや圧力調整器を介して排気装置1025と接続されている。
図5(A)に、ALD装置を用いた成膜シーケンスを示す。まず、チャンバー1020内の基板ホルダ1026に基板1030をセットする(S101)。次に、ヒータ1027の温度調節を行う(S102)。次に、基板1030の温度が基板面内で一様になるように基板1030を基板ホルダ1026に保持する(S103)。次に、チャンバー1020内部を酸素雰囲気にする(S104)。次に、上述の第1ステップ乃至第4ステップにより、成膜を行う。すなわち、チャンバー1020に第1の原料ガス、および第2の原料ガスを交互に導入し、基板1030上に成膜を行う(S105)。基板1030のセット、および保持後に、チャンバー1020内部を酸素雰囲気とすることで、基板1030および基板1030上に設けられた膜に酸素を添加できる場合がある。また、基板1030および基板1030上に設けられた膜から水素を脱離できる場合がある。基板1030中、または膜中の水素が、基板1030中、または膜中に添加された酸素と反応し、水(H2O)となって基板1030、または膜から離脱する場合がある。
ここで、本実施の形態のセルアレイの一例を、図6および図7に示す。図6および図7では、トランジスタ200、および容量素子100を有するセル600を、マトリクス状に配置することで、セルアレイを構成することができる。なお、トランジスタ200(トランジスタ200a、トランジスタ200b)は図1で示したトランジスタ200や、図3で示したトランジスタ201を用いることができる。
ここで、本実施の形態のセルアレイの一例を、図8および図9に示す。図8および図9では、トランジスタ200、および容量素子100を有するセル600、およびセル600と電気的に接続するトランジスタ300を、マトリクス状に配置することで、セルアレイを構成することができる。なお、トランジスタ200(トランジスタ200a、トランジスタ200b)は図1で示したトランジスタ200や、図3で示したトランジスタ201を用いることができる。
図10は、トランジスタ400の一態様を示す断面模式図である。トランジスタ400は、トランジスタ200と異なる構造を有していてもよい。
以下では、半導体装置に用いることができる構成材料について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばSOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を1種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物230として、酸化物半導体として機能する金属酸化物(以下、酸化物半導体ともいう)を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud-Aligned Composite)-OSの構成について説明する。
酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC-OS(c-axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc-OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a-like OS:amorphous-like oxide semiconductor)および非晶質酸化物半導体などがある。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
次に、本発明に係るトランジスタ200を有する半導体装置について、作製方法を図11乃至図22を用いて説明する。また、図11乃至図22において、各図の(A)は上面図を示す。また、各図の(B)は(A)に示すA-Bの一点鎖線で示す部位に対応する断面図である。また、各図の(C)は、(A)にC-Dの一点鎖線で示す部位に対応する断面図である。また、各図の(D)は、(A)にE-Fの一点鎖線で示す部位に対応する断面図である。
トランジスタ201と同じ層に、容量素子100を有する半導体装置について、作製方法を図23乃至図25を用いて説明する。また、図23乃至図25において、各図の(A)は上面図を示す。また、各図の(B)は(A)に示すA-Bの一点鎖線で示す部位に対応する断面図である。また、各図の(C)は、(A)にC-Dの一点鎖線で示す部位に対応する断面図である。また、各図の(D)は、(A)にE-Fの一点鎖線で示す部位に対応する断面図である。
本実施の形態では、半導体装置の一形態を、図26乃至図29を用いて説明する。
図26(A)および図27に示す記憶装置は、トランジスタ200、容量素子100、およびトランジスタ300と、を有している。
本発明の一態様の記憶装置は、図26(A)および図27に示すようにトランジスタ300、トランジスタ200、容量素子100を有する。トランジスタ200はトランジスタ300の上方に設けられ、容量素子100はトランジスタ200と同じ層に設けられている。
また、本実施の形態の変形例を、図28、および図29に示す。
本実施の形態では、図30乃至図33を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ。)、および容量素子が適用されている記憶装置の一例として、NOSRAMについて説明する。NOSRAM(登録商標)とは「Nonvolatile Oxide Semiconductor RAM」の略称であり、ゲインセル型(2T型、3T型)のメモリセルを有するRAMを指す。なお、以下において、NOSRAMのようにOSトランジスタを用いたメモリ装置を、OSメモリと呼ぶ場合がある。
図30にNOSRAMの構成例を示す。図30に示すNOSRAM1600は、メモリセルアレイ1610、コントローラ1640、行ドライバ1650、列ドライバ1660、出力ドライバ1670を有する。なお、NOSRAM1600は、1のメモリセルで多値データを記憶する多値NOSRAMである。
図31(A)はメモリセル1611の構成例を示す回路図である。メモリセル1611は2T型のゲインセルであり、メモリセル1611はワード線WWL、RWL、ビット線BL、ソース線SL、配線BGLに電気的に接続されている。メモリセル1611は、ノードSN、OSトランジスタMO61、トランジスタMP61、容量素子C61を有する。OSトランジスタMO61は書き込みトランジスタである。トランジスタMP61は読み出しトランジスタであり、例えばpチャネル型Siトランジスタで構成される。容量素子C61はノードSNの電圧を保持するための保持容量である。ノードSNはデータの保持ノードであり、ここではトランジスタMP61のゲートに相当する。
本実施の形態では、図34および図35を用いて、本発明の一態様に係る、OSトランジスタ、および容量素子が適用されている記憶装置の一例として、DOSRAMについて説明する。DOSRAM(登録商標)とは、「Dynamic Oxide Semiconductor RAM」の略称であり、1T(トランジスタ)1C(容量)型のメモリセルを有するRAMを指す。DOSRAMも、NOSRAMと同様に、OSメモリが適用されている。
図34にDOSRAMの構成例を示す。図34に示すように、DOSRAM1400は、コントローラ1405、行回路1410、列回路1415、メモリセルおよびセンスアンプアレイ1420(以下、「MC-SAアレイ1420」と呼ぶ。)を有する。
MC-SAアレイ1420は、メモリセルアレイ1422をセンスアンプアレイ1423上に積層した積層構造をもつ。グローバルビット線GBLL、GBLRはメモリセルアレイ1422上に積層されている。DOSRAM1400では、ビット線の構造に、ローカルビット線とグローバルビット線とで階層化された階層ビット線構造が採用されている。
コントローラ1405は、DOSRAM1400の動作全般を制御する機能を有する。コントローラ1405は、外部からの入力されるコマンド信号を論理演算して、動作モードを決定する機能、決定した動作モードが実行されるように、行回路1410、列回路1415の制御信号を生成する機能、外部から入力されるアドレス信号を保持する機能、内部アドレス信号を生成する機能を有する。
行回路1410は、MC-SAアレイ1420を駆動する機能を有する。デコーダ1411はアドレス信号をデコードする機能を有する。ワード線ドライバ回路1412は、アクセス対象行のワード線WLを選択する選択信号を生成する。
列回路1415は、データ信号WDA[31:0]の入力を制御する機能、データ信号RDA[31:0]の出力を制御する機能を有する。データ信号WDA[31:0]は書き込みデータ信号であり、データ信号RDA[31:0]は読み出しデータ信号である。
本実施の形態では、図36から図39を用いて、本発明の一態様に係る、OSトランジスタ、および容量素子が適用されている半導体装置の一例として、FPGA(フィールドプログラマブルゲートアレイ)について説明する。本実施の形態のFPGAは、コンフィギュレーションメモリ、およびレジスタにOSメモリが適用されている。ここでは、このようなFPGAを「OS-FPGA」と呼ぶ。
図36(A)にOS-FPGAの構成例を示す。図36(A)に示すOS-FPGA3110は、マルチコンテキスト構造によるコンテキスト切り替え、細粒度パワーゲーティング、NOFF(ノーマリオフ)コンピューティングが可能である。OS-FPGA3110は、コントローラ(Controller)3111、ワードドライバ(Word driver)3112、データドライバ(Data driver)3113、プログラマブルエリア(Programmable area)3115を有する。
“H”の信号storeがOS-FF3140に入力されると、シャドウレジスタ3142はFF3141のデータをバックアップする。ノードN36は、ノードQのデータが書き込まれることで、“L”となり、ノードNB36は、ノードQBのデータが書き込まれることで、“H”となる。しかる後、パワーゲーティングが実行され、パワースイッチ3127をオフにする。FF3141のノードQ、QBのデータは消失するが、電源オフであっても、シャドウレジスタ3142はバックアップしたデータを保持する。
パワースイッチ3127をオンにし、PLE3121に電源を供給する。しかる後、“H”の信号loadがOS-FF3140に入力されると、シャドウレジスタ3142はバックアップしているデータをFF3141に書き戻す。ノードN36は“L”であるので、ノードN37は“L”が維持され、ノードNB36は“H”であるので、ノードNB37は“H”となる。よって、ノードQは“H”になり、ノードQBは“L”になる。つまり、OS-FF3140はバックアップ動作時の状態に復帰する。
本実施の形態では、図40を用いて、上記実施の形態に示す半導体装置を適用した、AIシステムについて説明を行う。
<AIシステムの応用例>
本実施の形態では、上記実施の形態に示すAIシステムの応用例について図41を用いて説明を行う。
本実施の形態は、上記実施の形態に示すAIシステムが組み込まれたICの一例を示す。
<電子機器>
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図43に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。
100a 容量素子
100b 容量素子
130 導電体
130a 導電体
130A 導電膜
130b 導電体
130B 導電膜
200 トランジスタ
200a トランジスタ
200b トランジスタ
201 トランジスタ
203 導電体
205 導電体
207 導電体
208 絶縁体
209 導電体
210 絶縁体
212 絶縁体
214 絶縁体
216 絶縁体
220 絶縁体
222 絶縁体
222a 絶縁体
222b 絶縁体
222c 絶縁体
224 絶縁体
230 酸化物
230a 酸化物
230A 酸化膜
230b 酸化物
230B 酸化膜
230c 酸化物
230C 酸化膜
230d 酸化物
231 領域
231a 領域
231b 領域
232 領域
232a 領域
232b 領域
234 領域
239 領域
250 絶縁体
250a 絶縁体
250A 絶縁膜
250b 絶縁体
250B 絶縁膜
252 導電体
252a 導電体
252b 導電体
252c 導電体
252d 導電体
256 導電体
260 導電体
260a 導電体
260A 導電膜
260b 導電体
260B 導電膜
270 絶縁体
270A 絶縁膜
271 絶縁体
271A 絶縁膜
272 絶縁体
272A 絶縁膜
273 絶縁体
273A 絶縁膜
274 絶縁体
276 絶縁体
276a 絶縁体
276b 絶縁体
276c 絶縁体
280 絶縁体
300 トランジスタ
300a トランジスタ
300b トランジスタ
311 基板
313 半導体領域
314a 低抵抗領域
314b 低抵抗領域
315 絶縁体
316 導電体
320 絶縁体
322 絶縁体
324 絶縁体
326 絶縁体
328 導電体
330 導電体
350 絶縁体
352 絶縁体
354 絶縁体
356 導電体
360 絶縁体
362 絶縁体
364 絶縁体
366 導電体
370 絶縁体
372 絶縁体
374 絶縁体
376 導電体
380 絶縁体
382 絶縁体
384 絶縁体
386 導電体
400 トランジスタ
403 導電体
405 導電体
409 導電体
430 酸化物
430a 酸化物
430b 酸化物
430c 酸化物
430d 酸化物
450 絶縁体
450a 絶縁体
450b 絶縁体
452a 導電体
452b 導電体
460 導電体
460a 導電体
460b 導電体
470 絶縁体
471 絶縁体
472 絶縁体
473 絶縁体
600 セル
600a セル
600b セル
620 回路
640 回路
830 モニタ
831 表示部
832 筐体
833 スピーカ
834 リモコン操作機
860 ナビゲーション装置
861 表示部
862 操作ボタン
863 外部入力端子
1000 成膜装置
1002 搬入搬出室
1004 搬入搬出室
1006 搬送室
1008 成膜室
1009 成膜室
1010 成膜室
1014 搬送アーム
1020 チャンバー
1021a 原料供給部
1021b 原料供給部
1022a 高速バルブ
1022b 高速バルブ
1023a 原料導入口
1023b 原料導入口
1024 原料排出口
1025 排気装置
1026 基板ホルダ
1027 ヒータ
1028 プラズマ発生装置
1029 コイル
1030 基板
1400 DOSRAM
1405 コントローラ
1410 行回路
1411 デコーダ
1412 ワード線ドライバ回路
1413 列セレクタ
1414 センスアンプドライバ回路
1415 列回路
1416 グローバルセンスアンプアレイ
1417 入出力回路
1420 センスアンプアレイ
1422 メモリセルアレイ
1423 センスアンプアレイ
1425 ローカルメモリセルアレイ
1426 ローカルセンスアンプアレイ
1444 スイッチアレイ
1445 メモリセル
1446 センスアンプ
1447 グローバルセンスアンプ
1600 NOSRAM
1610 メモリセルアレイ
1611 メモリセル
1612 メモリセル
1613 メモリセル
1614 メモリセル
1615 メモリセル
1615a メモリセル
1615b メモリセル
1640 コントローラ
1650 行ドライバ
1651 行デコーダ
1652 ワード線ドライバ
1660 列ドライバ
1661 列デコーダ
1662 ドライバ
1663 DAC
1670 出力ドライバ
1671 セレクタ
1672 ADC
1673 出力バッファ
2000 CDMA
2910 情報端末
2911 筐体
2912 表示部
2913 カメラ
2914 スピーカ部
2915 操作スイッチ
2916 外部接続部
2917 マイク
2920 ラップトップ型パーソナルコンピュータ
2921 筐体
2922 表示部
2923 キーボード
2924 ポインティングデバイス
2940 ビデオカメラ
2941 筐体
2942 筐体
2943 表示部
2944 操作スイッチ
2945 レンズ
2946 接続部
2980 自動車
2981 車体
2982 車輪
2983 ダッシュボード
2984 ライト
3001 配線
3002 配線
3003 配線
3004 配線
3005 配線
3006 配線
3110 OS-FPGA
3111 コントローラ
3112 ワードドライバ
3113 データドライバ
3115 プログラマブルエリア
3117 IOB
3119 コア
3120 LAB
3121 PLE
3123 LUTブロック
3124 レジスタブロック
3125 セレクタ
3126 CM
3127 パワースイッチ
3128 CM
3130 SAB
3131 SB
3133 PRS
3135 CM
3137 メモリ回路
3137B メモリ回路
3140 OS-FF
3141 FF
3142 シャドウレジスタ
3143 メモリ回路
3143B メモリ回路
3188 インバータ回路
3189 インバータ回路
4010 演算部
4011 アナログ演算回路
4012 DOSRAM
4013 NOSRAM
4014 FPGA
4020 制御部
4021 CPU
4022 GPU
4023 PLL
4025 PROM
4026 メモリコントローラ
4027 電源回路
4028 PMU
4030 入出力部
4031 外部記憶制御回路
4032 音声コーデック
4033 映像コーデック
4034 汎用入出力モジュール
4035 通信モジュール
4041 AIシステム
4041_n AIシステム
4041_1 AIシステム
4041A AIシステム
4041B AIシステム
4098 バス線
4099 ネットワーク
7000 AIシステムIC
7001 リード
7003 回路部
7031 Siトランジスタ層
7032 配線層
7033 OSトランジスタ層
Claims (3)
- 酸化物が設けられた基板を成膜室にセットし、
前記成膜室に酸化剤をパルス状に複数回導入し、
前記酸化剤の導入後に、前記酸化物上にALD法を用いて絶縁膜を形成し、
前記酸化剤の導入により、前記酸化物への酸素の添加と、前記酸化物から水素または水の脱離と、の一方、または両方を行う、半導体装置の作製方法。 - 酸化物が設けられた基板を成膜室にセットし、
前記成膜室に酸化剤をパルス状に複数回導入し、
前記酸化剤の導入後に、前記酸化物上に絶縁膜を形成し、
前記酸化剤の導入により、前記酸化物への酸素の添加と、前記酸化物から水素または水の脱離と、の一方、または両方を行う工程を有し、
前記絶縁膜は、アルミニウムおよびハフニウムの一方または両方を含む酸化物である、半導体装置の作製方法。 - 請求項2において、
前記絶縁膜は、ALD法を用いて形成される、半導体装置の作製方法。
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PCT/IB2018/052617 WO2018197988A1 (ja) | 2017-04-28 | 2018-04-16 | 半導体装置、および半導体装置の作製方法 |
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