JPWO2016114055A1 - 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置および炭化珪素半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 178
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- 239000000377 silicon dioxide Substances 0.000 claims abstract description 8
- 239000010936 titanium Substances 0.000 claims description 42
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 41
- 229910052719 titanium Inorganic materials 0.000 claims description 41
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Abstract
Description
実施の形態1にかかる炭化珪素半導体装置の構造について、プレーナーゲート構造のSiC−縦型MOSFETを例に説明する。図1は、実施の形態1にかかる炭化珪素半導体装置の構造を示す断面図である。図1には、電流駆動を担う活性領域(オン状態のときに電流が流れる領域)の1つの単位セル(素子の機能単位)を示し、この単位セルに隣接するように繰り返し配置された他の単位セルや、活性領域の周囲を囲む耐圧構造部を図示省略する(図2,3においても同様)。耐圧構造部は、n-型ドリフト層2の基体おもて面側の電界を緩和し耐圧を保持する領域であり、例えばガードリング、フィールドプレートおよびリサーフ等を組み合わせた耐圧構造を有する。
次に、実施の形態2にかかる炭化珪素半導体装置の構造について説明する。図2は、実施の形態2にかかる炭化珪素半導体装置の構造を示す断面図である。実施の形態2にかかる炭化珪素半導体装置が実施の形態1にかかる炭化珪素半導体装置と異なる点は、ポリシリコン膜16とソース電極12との間に、チタン(Ti)を主成分とする金属膜(以下、チタン膜とする)15が設けられている点である。チタン膜15は、ソース電極12中から発生する水素原子・水素イオンを遮蔽する機能を有する。すなわち、チタン膜15中における水素原子・水素イオンの拡散係数は、チタン膜15中を移動する水素原子・水素イオンが下層のポリシリコン膜16にほぼ達しない程度に小さい。
次に、実施の形態3にかかる炭化珪素半導体装置の構造について説明する。図3は、実施の形態3にかかる炭化珪素半導体装置の構造を示す断面図である。実施の形態3にかかる炭化珪素半導体装置が実施の形態2にかかる炭化珪素半導体装置と異なる点は、チタン膜(以下、第1チタン膜とする)15とソース電極12との間に、窒化チタン(TiN)を主成分とする金属膜(以下、窒化チタン膜とする)17や第2チタン膜18が設けられている点である。窒化チタン膜17および第2チタン膜18は、ソース電極12中から発生する水素原子・水素イオンを吸蔵する機能を有する。
次に、従来のSiC−MOSFET(以下、従来例とする図6参照)においてしきい値電圧変動が生じる原因について説明する。従来例においてSiO2/SiC界面の界面準位密度が高いのは、SiO2/SiC界面に特有の問題であり、SiO2/SiC界面の欠陥量、歪量およびバンド構造の違いから生じるかは現時点では明らかではない。そこで、各電極層として形成されるアルミニウム層の配置を種々変更して、従来例のしきい値電圧変動の原因について検証した。図4は、比較例1の炭化珪素半導体装置の構造を示す断面図である。図5は、比較例2の炭化珪素半導体装置の構造を示す断面図である。図4に示すように、層間絶縁膜30上に電極層(アルミニウム層)を配置しない、かつコンタクトホールにおいて電極層と層間絶縁膜30とが接触しない構成のプレーナーゲート構造のSiC−横型MOSFETを作製した(以下、比較例1とする)。
2 n-型ドリフト層
3 p型半導体領域
4 p-型ウエル層
5 p+型コンタクト領域
6 n+型ソース領域
7 JFET領域
8 ゲート絶縁膜
9 ゲート電極
10 層間絶縁膜
11 ニッケルシリサイド層
12 ソース電極(アルミニウム層)
13 裏面電極
14 パッシベーション保護膜
15 チタン膜(第1チタン膜)
16 ポリシリコン膜
17 窒化チタン膜
18 第2チタン膜
Claims (9)
- 炭化珪素半導体部に接する二酸化珪素膜をゲート絶縁膜とする絶縁ゲート構造と、
前記絶縁ゲート構造を覆う層間絶縁膜と、
前記層間絶縁膜の表面に設けられたポリシリコン膜と、
前記ポリシリコン膜の表面に設けられ、かつ前記炭化珪素半導体部に電気的に接続された第1主電極と、
を備えることを特徴とする炭化珪素半導体装置。 - 前記ポリシリコン膜と前記第1主電極との間に設けられた第1チタン膜をさらに備えることを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記第1チタン膜と前記第1主電極との間に設けられた窒化チタン膜をさらに備えることを特徴とする請求項2に記載の炭化珪素半導体装置。
- 前記窒化チタン膜と前記第1主電極との間に設けられた第2チタン膜をさらに備えることを特徴とする請求項3に記載の炭化珪素半導体装置。
- 前記ポリシリコン膜の厚さは、0.2μm以上1.0μm以下であることを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記ポリシリコン膜の厚さは、0.5μm以上であることを特徴とする請求項5に記載の炭化珪素半導体装置。
- 炭化珪素半導体からなる半導体基板と、
前記半導体基板の一方の主面に設けられた、炭化珪素半導体からなるn型ドリフト層と、
前記n型ドリフト層の、前記半導体基板側に対して反対側に選択的に設けられ、前記炭化珪素半導体部を構成するp型半導体領域と、
前記p型半導体領域の内部に選択的に設けられ、前記炭化珪素半導体部を構成するn型半導体領域と、
前記p型半導体領域の、前記n型ドリフト層と前記n型半導体領域とに挟まれた部分の表面上に設けられた前記ゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられ、前記絶縁ゲート構造を構成するゲート電極と、
前記n型半導体領域に電気的に接続された前記第1主電極と、
前記半導体基板の他方の主面に設けられた第2主電極と、
を備えることを特徴とする請求項1〜6のいずれか一つに記載の炭化珪素半導体装置。 - 前記半導体基板はn型であり、前記n型ドリフト層よりも不純物濃度が高いことを特徴とする請求項7に記載の炭化珪素半導体装置。
- 炭化珪素半導体部を熱酸化して、前記炭化珪素半導体部の表面に二酸化珪素膜を形成する工程と、
前記二酸化珪素膜をゲート絶縁膜とする絶縁ゲート構造を形成する工程と、
前記絶縁ゲート構造を覆う層間絶縁膜を形成する工程と、
前記層間絶縁膜の上にポリシリコン膜を形成する工程と、
前記ポリシリコン膜の上に、前記炭化珪素半導体部に電気的に接続されるように第1主電極を形成する工程と、
を含むことを特徴とする炭化珪素半導体装置の製造方法。
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