JPWO2016080269A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Abstract
Description
実施の形態1にかかる半導体装置の構造について説明する。図1は、実施の形態1にかかる半導体装置の構造を示す断面図である。図1に示すように、実施の形態1にかかる半導体装置は、n-型ドリフト層1となる同一のn-型半導体基板(半導体チップ)上に、IGBTを配置したIGBT部(第1素子領域)21と、FWDを配置したFWD部(第2素子領域)22とを備える。IGBT部21のIGBTとして、例えばn型フィールドストップ層10を備えたFS−IGBTを配置した場合を例に説明する。FWD部22のFWDは、IGBT部21のFS−IGBTに逆並列に接続されている。すなわち、実施の形態1にかかる半導体装置は、FS−IGBTとFWDとを同一半導体チップに内蔵して一体化したRC−IGBTである。
次に、実施の形態2にかかる半導体装置の製造方法について、図7〜11を参照して説明する。図7は、実施の形態2にかかる半導体装置の製造方法の概要を示すフローチャートである。図8〜11は、実施の形態2にかかる半導体装置の製造途中の状態を示す断面図である。実施の形態2にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、第1,2コンタクトホール9a,9bを異なるマスクを用いて形成する点である。実施の形態2にかかる半導体装置の製造方法は、図1に示すRC−IGBTを作製(製造)するための別の一例である。
実施の形態3にかかる半導体装置の製造方法について説明する。図12は、実施の形態3にかかる半導体装置の構造を示す断面図である。実施の形態3にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、IGBT部21およびFWD部22ともにデザインルールを微細化している点である。具体的には、例えば、IGBT部21およびFWD部22を同一のデザインルールで微細化してもよい。すなわち、IGBT部21からFWD部22にわたって同じピッチ(W11=W12)でトレンチ3を設け、かつ第1,2コンタクトホール9a,9bの幅(第1方向の幅)W21,W22を等しくしてもよい(W21=W22)。IGBT部21およびFWD部22の寸法は、例えば、実施の形態1のIGBT部21と同様であってもよい。
次に、本発明にかかるRC−IGBTの順方向電圧(Vf)特性について検証した。図16は、実施例にかかる半導体装置の順方向電圧特性を示す特性図である。上述した実施の形態1にかかる半導体装置の製造方法にしたがい、微細化されたデザインルールで構成されたRC−IGBTを作製(製造)した(以下、実施例とする)。すなわち、実施例は、IGBT部においてコンタクトプラグを介してエミッタ電極と半導体部とを電気的に接続し、FWD部においてエミッタ電極と半導体部とを直接接続した構成となっている。
2 p型ベース領域
3 トレンチ
4 ゲート絶縁膜
5 ゲート電極
6 n+型エミッタ領域
7 p+型コンタクト領域(第1p+型コンタクト領域)
8 エミッタ電極
9 層間絶縁膜
9a 第1コンタクトホール
9b 第2コンタクトホール
10 n型フィールドストップ層
11 p+型コレクタ領域
12 n+型カソード領域
13 コレクタ電極
14 コンタクトプラグ
15 チタン層
16 窒化チタン層
17 タングステン層
18 第2p+型コンタクト領域
20 MOSゲート構造
21 IGBT部
22 FWD部
23 中間領域
31〜34 レジストマスク
35 イオン注入
W11 IGBT部のトレンチのピッチ
W12 FWD部のトレンチのピッチ
W21 第1コンタクトホールの幅
W22 第2コンタクトホールの幅
Claims (13)
- 第1導電型のドリフト層となる半導体基板に、絶縁ゲート型バイポーラトランジスタが設けられた第1素子領域と、ダイオードが設けられた第2素子領域と、を備えた半導体装置であって、
前記半導体基板のおもて面に、前記第1素子領域から前記第2素子領域にわたって設けられた複数のトレンチと、
前記複数のトレンチの少なくとも一部のトレンチの内部に、ゲート絶縁膜を介して設けられたゲート電極と、
前記第1素子領域の隣り合う前記トレンチの間に設けられた第2導電型のベース領域と、
前記第2素子領域の隣り合う前記トレンチの間に設けられた第2導電型のアノード領域と、
前記ベース領域の内部に選択的に設けられた第1導電型のエミッタ領域と、
前記ベース領域の内部に選択的に設けられた、前記ベース領域よりも不純物濃度の高い第2導電型の第1コンタクト領域と、
前記ゲート電極を覆う層間絶縁膜と、
前記層間絶縁膜を深さ方向に貫通して前記エミッタ領域および前記第1コンタクト領域を露出する第1コンタクトホールと、
前記層間絶縁膜を深さ方向に貫通して前記アノード領域を露出する第2コンタクトホールと、
前記第1コンタクトホールに埋め込まれ、前記エミッタ領域および前記第1コンタクト領域に接するコンタクトプラグと、
前記コンタクトプラグに接し、かつ前記第2コンタクトホールに埋め込まれて前記アノード領域に接する第1電極と、
前記第1素子領域において前記半導体基板の裏面に設けられた第2導電型のコレクタ領域と、
前記第2素子領域において前記半導体基板の裏面に設けられた第1導電型のカソード領域と、
前記コレクタ領域および前記カソード領域に接する第2電極と、
を備えることを特徴とする半導体装置。 - 前記コンタクトプラグは、少なくとも、
前記エミッタ領域および前記第1コンタクト領域に接するチタン層と、
前記第1電極に接するタングステン層と、からなることを特徴とする請求項1に記載の半導体装置。 - 前記第1電極は、アルミニウムを主成分とする金属からなることを特徴とする請求項1に記載の半導体装置。
- 前記第2コンタクトホールの、前記第1素子領域と前記第2素子領域とが並ぶ方向における幅は、前記第1コンタクトホールの、前記第1素子領域と前記第2素子領域とが並ぶ方向における幅よりも広いことを特徴とする請求項1に記載の半導体装置。
- 前記第2素子領域の隣り合う前記トレンチ間の間隔は、前記第1素子領域の隣り合う前記トレンチ間の間隔よりも広いことを特徴とする請求項1に記載の半導体装置。
- 前記アノード領域の内部に選択的に設けられた、前記アノード領域よりも不純物濃度の高い第2導電型の第2コンタクト領域をさらに備えることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
- 前記第2コンタクトホールに前記コンタクトプラグが埋め込まれており、
前記第1電極は、前記コンタクトプラグを介して前記第2コンタクト領域に電気的に接続されていることを特徴とする請求項6に記載の半導体装置。 - 第1導電型のドリフト層となる半導体基板に、絶縁ゲート型バイポーラトランジスタが設けられた第1素子領域と、ダイオードが設けられた第2素子領域と、を備え、前記絶縁ゲート型バイポーラトランジスタのおもて面素子構造として、前記半導体基板のおもて面に、前記第1素子領域から前記第2素子領域にわたって設けられた複数のトレンチと、前記複数のトレンチの少なくとも一部のトレンチの内部に、ゲート絶縁膜を介して設けられたゲート電極と、前記第1素子領域の隣り合う前記トレンチの間に設けられた第2導電型のベース領域と、前記ベース領域の内部に選択的に設けられた第1導電型のエミッタ領域と、前記ベース領域の内部に選択的に設けられた、前記ベース領域よりも不純物濃度の高い第2導電型の第1コンタクト領域と、を有し、前記ダイオードのおもて面素子構造として、前記トレンチと、前記ゲート電極と、前記第2素子領域の隣り合う前記トレンチの間に設けられた第2導電型のアノード領域と、を有する半導体装置の製造方法であって、
前記半導体基板のおもて面側に、前記絶縁ゲート型バイポーラトランジスタおよび前記ダイオードの前記おもて面素子構造を形成する第1形成工程と、
前記おもて面素子構造を覆う層間絶縁膜を形成する第2形成工程と、
前記層間絶縁膜を貫通して前記エミッタ領域および前記第1コンタクト領域を露出する第1コンタクトホールを形成するとともに、前記層間絶縁膜を深さ方向に貫通して前記アノード領域を露出し、かつ前記第1素子領域と前記第2素子領域とが並ぶ方向における幅が前記第1コンタクトホールよりも広い第2コンタクトホールを形成する第3形成工程と、
前記第1コンタクトホールに埋め込むように、前記半導体基板のおもて面に金属層を堆積させる堆積工程と、
前記金属層をエッチバックし、前記層間絶縁膜の表面および前記第2コンタクトホールの内部の前記金属層を除去するとともに、前記第1コンタクトホールの内部の前記金属層を前記エミッタ領域および前記第1コンタクト領域とのコンタクトプラグとして残す除去工程と、
前記コンタクトプラグに接し、かつ前記第2コンタクトホールに埋め込むように第1電極を形成する電極形成工程と、
を含むことを特徴とする半導体装置の製造方法。 - 第1導電型のドリフト層となる半導体基板に、絶縁ゲート型バイポーラトランジスタが設けられた第1素子領域と、ダイオードが設けられた第2素子領域と、を備え、前記絶縁ゲート型バイポーラトランジスタのおもて面素子構造として、前記半導体基板のおもて面に、前記第1素子領域から前記第2素子領域にわたって設けられた複数のトレンチと、前記複数のトレンチの少なくとも一部のトレンチの内部に、ゲート絶縁膜を介して設けられたゲート電極と、前記第1素子領域の隣り合う前記トレンチの間に設けられた第2導電型のベース領域と、前記ベース領域の内部に選択的に設けられた第1導電型のエミッタ領域と、前記ベース領域の内部に選択的に設けられた、前記ベース領域よりも不純物濃度の高い第2導電型の第1コンタクト領域と、を有し、前記ダイオードのおもて面素子構造として、前記トレンチと、前記ゲート電極と、前記第2素子領域の隣り合う前記トレンチの間に設けられた第2導電型のアノード領域と、を有する半導体装置の製造方法であって、 前記半導体基板のおもて面側に、前記絶縁ゲート型バイポーラトランジスタおよび前記ダイオードの前記おもて面素子構造を形成する第1形成工程と、
前記おもて面素子構造を覆う層間絶縁膜を形成する第2形成工程と、
前記層間絶縁膜を貫通して前記エミッタ領域および前記第1コンタクト領域を露出する第1コンタクトホールを形成するとともに、前記層間絶縁膜を深さ方向に貫通して前記アノード領域を露出する第2コンタクトホールを形成する第3形成工程と、
前記第2コンタクトホールに露出する前記アノード領域の内部に、前記アノード領域よりも不純物濃度の高い第2導電型の第2コンタクト領域を選択的に形成する第4形成工程と、
前記第1コンタクトホールおよび前記第2コンタクトホールに埋め込むように、前記半導体基板のおもて面に金属層を堆積させる堆積工程と、
前記金属層をエッチバックして前記層間絶縁膜の表面の前記金属層を除去し、前記第1コンタクトホールの内部の前記金属層を前記エミッタ領域および前記第1コンタクト領域との第1コンタクトプラグとして残すとともに、前記第2コンタクトホールの内部の前記金属層を前記アノード領域との第2コンタクトプラグとして残す除去工程と、
前記第1コンタクトプラグおよび前記第2コンタクトプラグに接する第1電極を形成する電極形成工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第3形成工程では、前記第1コンタクトホールおよび前記第2コンタクトホールの、前記第1素子領域と前記第2素子領域とが並ぶ方向における幅を等しくすることを特徴とする請求項9に記載の半導体装置の製造方法。
- 前記第4形成工程では、フッ化ホウ素をイオン注入して前記第2コンタクト領域を形成することを特徴とする請求項9に記載の半導体装置の製造方法。
- 前記堆積工程では、前記金属層として、少なくともチタン層およびタングステン層を順に堆積することを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記電極形成工程では、アルミニウムを主成分とする前記第1電極を形成することを特徴とする請求項8〜12のいずれか一つに記載の半導体装置の製造方法。
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US9911733B2 (en) | 2018-03-06 |
CN106463504B (zh) | 2019-11-29 |
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JP6566068B2 (ja) | 2019-08-28 |
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