JPWO2014118916A1 - Manufacturing method of component-embedded substrate - Google Patents

Manufacturing method of component-embedded substrate Download PDF

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JPWO2014118916A1
JPWO2014118916A1 JP2014559414A JP2014559414A JPWO2014118916A1 JP WO2014118916 A1 JPWO2014118916 A1 JP WO2014118916A1 JP 2014559414 A JP2014559414 A JP 2014559414A JP 2014559414 A JP2014559414 A JP 2014559414A JP WO2014118916 A1 JPWO2014118916 A1 JP WO2014118916A1
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component
window
metal plate
pattern
forming
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圭男 今村
圭男 今村
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Meiko Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom

Abstract

本発明の部品内蔵基板（１６）の製造方法は、金属板（１）の表面に前記金属板（１）に用いられた金属材料とは異なる導電金属材料を用いて導体パターン（４）及びビアの一部分となるべきビアウインドを形成するパターン及びビアウインド形成工程と、前記ビアウインドを覆うように接着剤（６）を塗布し、該接着剤（６）を介して前記ビアウインド上に端子（８）を配して電気又は電子的な部品（７）を搭載する部品搭載工程と、前記ビアウインドを通って前記端子（８）まで到達するビアを形成するビア形成工程と、前記ビアに対してめっき処理を施し、金属材料を充填して導通ビア（１４）とする導通ビア形成工程と、前記金属板（１）を除去して前記導体パターン（４）を露出させるパターン露出工程とを備えた。The method for manufacturing a component-embedded substrate (16) according to the present invention uses a conductive metal material different from the metal material used for the metal plate (1) on the surface of the metal plate (1). A pattern for forming a via window to be a part of the pattern and a via window forming step, and an adhesive (6) is applied so as to cover the via window, and terminals (on the via window via the adhesive (6)) 8), a component mounting step for mounting an electrical or electronic component (7), a via formation step for forming a via reaching the terminal (8) through the via window, and the via A conductive via forming step of performing a plating process and filling the metal material to form a conductive via (14); and a pattern exposing step of removing the metal plate (1) to expose the conductive pattern (4). It was.

Description

本発明は、部品内蔵基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a component-embedded substrate.

部品内蔵基板は、製品たる基板の内部に電気又は電子的な部品が内蔵されているため、部品が有する端子に向けて電気的接続を図るための導通経路を確保する必要がある。この導通を図るため、基板表面から端子に到達するビアを設け、ここに銅めっきを施すことにより基板外側と端子との導電性を確保している。このビアは、基板に部品を内蔵した後、端子めがけてレーザやドリル等を用いて設けられる。そしてその後に基板表面にパターンを形成する（例えば特許文献１参照）。   Since the component-embedded substrate has electrical or electronic components built into the product substrate, it is necessary to secure a conduction path for electrical connection toward the terminals of the component. In order to achieve this conduction, vias that reach the terminals from the substrate surface are provided, and copper plating is applied to the vias to secure the conductivity between the outside of the substrate and the terminals. The via is provided by using a laser, a drill, or the like toward the terminal after the component is built in the substrate. Then, a pattern is formed on the substrate surface (see, for example, Patent Document 1).

しかしながら、基板製造プロセスにおいてパターン形成を原因とする製品不良の割合は高いため、部品を内蔵した後にパターンを形成するとその割合の分だけ無駄な部品が必要となってしまう。部品には高価なものもあるため、部品内蔵後の製品不良は好ましくない。   However, since the rate of product defects due to pattern formation is high in the substrate manufacturing process, if a pattern is formed after the components are built in, unnecessary components corresponding to the proportion are required. Since some parts are expensive, defective products after the parts are built in are not preferable.

さらに、部品を内蔵した後にビアを形成することは、内蔵されて外側から端子の位置が明確に目視できない状態でビア形成を行うことになる。そのために位置合わせのためのマーク等を用いているが、さらなる位置決め精度が求められている。また、複数のビア形状も揃えた方が好ましいため、基板外側からビアを形成する際にはそれなりの技術を要する。   Furthermore, forming a via after incorporating a component forms the via in a state in which the position of the terminal cannot be clearly seen from the outside. For this purpose, a mark or the like for alignment is used, but further positioning accuracy is required. In addition, since it is preferable to arrange a plurality of via shapes, a certain technique is required when forming vias from the outside of the substrate.

特許第４５５１４６８号公報Japanese Patent No. 4551468

本発明は、上記従来技術を考慮したものであって、製品不良とともに無駄となる部品点数を極力減少させることができ、ビアの位置決め精度も向上して形状も揃えさせることができる部品内蔵基板の製造方法を提供することを目的とする。   The present invention takes the above-described conventional technology into consideration, and can reduce the number of parts that are wasted along with product defects as much as possible, improve the positioning accuracy of vias, and make the shape uniform. An object is to provide a manufacturing method.

前記目的を達成するため、本発明では、金属板の表面に前記金属板に用いられた金属材料とは異なる導電金属材料を用いて導体パターン及びビアの一部分となるべきビアウインドを形成するパターン及びビアウインド形成工程と、前記ビアウインドを覆うように接着剤を塗布し、該接着剤を介して前記ビアウインド上に端子を配して電気又は電子的な部品を搭載する部品搭載工程と、前記ビアウインドを通って前記端子まで到達するビアを形成するビア形成工程と、前記ビアに対してめっき処理を施し、金属材料を充填して導通ビアとする導通ビア形成工程と、前記金属板を除去して前記導体パターンを露出させるパターン露出工程とを備えたことを特徴とする部品内蔵基板の製造方法を提供する。   In order to achieve the above object, in the present invention, a conductive metal material different from the metal material used for the metal plate is formed on the surface of the metal plate, and a pattern for forming a conductor pattern and a via window to be a part of the via and A via window forming step, an adhesive is applied so as to cover the via window, and a component mounting step of mounting an electrical or electronic component by arranging a terminal on the via window via the adhesive; and A via forming step for forming a via reaching the terminal through the via window, a conductive via forming step for plating the via and filling the metal material to form a conductive via, and removing the metal plate And a pattern exposure step of exposing the conductor pattern. A method of manufacturing a component-embedded substrate is provided.

好ましくは、前記ビア形成工程の前に、前記金属板の一部を除去して前記ビアウインドを露出させるビアウインド露出工程をさらに備えた。   Preferably, the method further includes a via window exposing step of exposing the via window by removing a part of the metal plate before the via forming step.

好ましくは、前記ビア形成工程の前に、予め位置決めマークとして定めた前記導体パターンの一部を露出させるために前記金属板の一部を除去する位置決めマーク露出工程を備え、前記ビア形成工程にて、前記位置決めマークを基準として前記ビアを形成する。   Preferably, prior to the via forming step, a positioning mark exposing step of removing a part of the metal plate in order to expose a part of the conductor pattern determined as a positioning mark in advance, The via is formed with reference to the positioning mark.

本発明によれば、部品搭載工程に先だってパターン及びビアウインド形成工程を行うので、先に不具合が発生しやすいパターン形成を行うことになるため、部品を無駄に搭載することを抑制できる。また、このときにビアウインドも予め形成するので、外観から認識できる状態でビアの位置を定めることができ、ビアの位置決め精度が向上する。また、ビアの形状としても信頼性を向上させることができる。   According to the present invention, since the pattern and via window forming step is performed prior to the component mounting step, the pattern formation in which a defect is likely to occur is performed first, so that it is possible to suppress the unnecessary mounting of the component. At this time, since the via window is also formed in advance, the position of the via can be determined in a state where it can be recognized from the appearance, and the positioning accuracy of the via is improved. Also, the reliability of the via shape can be improved.

ビア形成の際に金属板の一部を除去してビアウインドを露出させておけば、孔あけの位置を視認することができるので、ビア形成の孔あけ位置精度をさらに向上させることができる。また、導体パターンの一部を位置決めマークとして用いてもビア形成の孔あけ位置精度の向上に寄与できる。   If a part of the metal plate is removed and the via window is exposed at the time of forming the via, the position of drilling can be visually recognized, so that the accuracy of the drilling position of via formation can be further improved. Further, even if a part of the conductor pattern is used as a positioning mark, it can contribute to improvement of the drilling position accuracy of via formation.

本発明の部品内蔵基板の製造方法を順番に示す説明図である。It is explanatory drawing which shows the manufacturing method of the component built-in board | substrate of this invention in order. 本発明の部品内蔵基板の製造方法を順番に示す説明図である。It is explanatory drawing which shows the manufacturing method of the component built-in board | substrate of this invention in order. 本発明の部品内蔵基板の製造方法を順番に示す説明図である。It is explanatory drawing which shows the manufacturing method of the component built-in board | substrate of this invention in order. 本発明の部品内蔵基板の製造方法を順番に示す説明図である。It is explanatory drawing which shows the manufacturing method of the component built-in board | substrate of this invention in order. 本発明の部品内蔵基板の製造方法を順番に示す説明図である。It is explanatory drawing which shows the manufacturing method of the component built-in board | substrate of this invention in order. 本発明の部品内蔵基板の製造方法を順番に示す説明図である。It is explanatory drawing which shows the manufacturing method of the component built-in board | substrate of this invention in order. 本発明の部品内蔵基板の製造方法を順番に示す説明図である。It is explanatory drawing which shows the manufacturing method of the component built-in board | substrate of this invention in order. ビアウインド露出工程の説明図である。It is explanatory drawing of a via window exposure process.

本発明に係る部品内蔵基板の製造方法を図１〜図７を参照して以下に説明する。
図１に示すように、金属製の金属板１の表面に金属膜２が貼り付けられた板体３を準備する。金属板１は例えばニッケルからなる。金属膜２は金属板１に用いられた金属材料（この例ではニッケル）とは異なる導電金属材料によって形成される。例えば銅である。このような異種金属からなる２層の板体３を用いて、パターン及びビアウインド形成工程を行う。A method for manufacturing a component-embedded substrate according to the present invention will be described below with reference to FIGS.
As shown in FIG. 1, a plate body 3 in which a metal film 2 is attached to the surface of a metal plate 1 is prepared. The metal plate 1 is made of nickel, for example. The metal film 2 is formed of a conductive metal material different from the metal material used in the metal plate 1 (in this example, nickel). For example, copper. A pattern and via window forming process is performed using such a two-layer plate 3 made of different metals.

この工程は、図２に示すように、金属板１上の金属膜２をエッチング処理することにより行う。具体的には銅箔である金属膜２にエッチングレジスト（不図示）を塗布し、露出している銅をエッチング溶液で溶かしながら除去して導体パターン４及びビアウインド５を形成する。いわゆるサブトラクティブ法である。このようにサブトラクティブ法を用いれば、もともと金属板１に貼り付けられた金属膜２が均一の厚さであるため、導体パターン４としても均一な導体厚を得ることができる。また、金属板１と金属膜２とは異種金属であるため、エッチングも選択的に行うことができ、種々の不良（例えば後述するマーク１１の消失や導体パターン４の消失等）を招くことを防止できる。ビアウインド５は後述する内蔵部品が有する端子に到達する孔であるビアの一部分となるべき孔が形成されたものである。例えば金属膜２を円環状にしたものが考えられる。   This step is performed by etching the metal film 2 on the metal plate 1 as shown in FIG. Specifically, an etching resist (not shown) is applied to the metal film 2 that is a copper foil, and the exposed copper is removed while being melted with an etching solution to form the conductor pattern 4 and the via window 5. This is a so-called subtractive method. When the subtractive method is used in this manner, the metal film 2 originally attached to the metal plate 1 has a uniform thickness, so that the conductor pattern 4 can have a uniform conductor thickness. Further, since the metal plate 1 and the metal film 2 are dissimilar metals, the etching can be selectively performed, which causes various defects (for example, disappearance of a mark 11 described later and disappearance of a conductor pattern 4). Can be prevented. The via window 5 is formed with a hole to be a part of a via that is a hole reaching a terminal included in a built-in component described later. For example, an annular metal film 2 can be considered.

このように、ビアウインド５を外観から認識できる状態で形成するので、将来ビア９（図５参照）となる位置を予め定めることができ、ビア９の位置決め精度が向上する。また、ビア９の形状としても信頼性を向上させることができる。   Thus, since the via window 5 is formed in a state where it can be recognized from the appearance, the position to be the via 9 (see FIG. 5) in the future can be determined in advance, and the positioning accuracy of the via 9 is improved. Also, the reliability of the shape of the via 9 can be improved.

なお、上記導体パターン４及びビアウインド５はセミアディティブ法を用いて形成してもよい。具体的には、ＳＵＳ板上にニッケルめっきを施し、その上にパターンに対応しためっきレジスト処理をした後、銅めっきを施す。この方法を用いれば、より高密度化した導体パターンに対応することができる。高密度という観点では、上記板体３が有する金属膜３はめっきではなく銅箔であるため、上記サブトラクティブ法でも高密度の導体パターン４を形成することは可能である。   The conductor pattern 4 and the via window 5 may be formed using a semi-additive method. Specifically, nickel plating is performed on the SUS plate, and after performing a plating resist treatment corresponding to the pattern thereon, copper plating is performed. If this method is used, it is possible to cope with a higher-density conductor pattern. From the viewpoint of high density, since the metal film 3 included in the plate 3 is not a plating but a copper foil, the high-density conductor pattern 4 can be formed even by the subtractive method.

次に、図３に示すように、部品搭載工程を行う。この工程では、ビアウインド５を覆うように接着剤６を塗布する。そして、接着剤６上に電気又は電子的な部品７を搭載する。このとき、ビアウインド５上に部品７が有する端子８が配置されるように搭載される。このように、ビアウインド５が部品搭載時に予め形成されているので、部品の実装精度はビアウインド５の孔と端子８との位置の整合精度となるので、高い実装精度を実現できる。また、部品搭載工程に先立ってパターン及びビアウインド形成工程を行っているので、先に不具合が発生しやすいパターン４の形成を行うことになるため、部品７を無駄に搭載することを抑制できる。換言すれば、先に回路形成を行っているので、部品７の実装時に回路不良箇所への部品搭載を回避することができる。また、ビアウインド５の高さを適宜設定することで、将来的なビア９の深さもある程度定めることができる。   Next, as shown in FIG. 3, a component mounting process is performed. In this step, the adhesive 6 is applied so as to cover the via window 5. Then, an electrical or electronic component 7 is mounted on the adhesive 6. At this time, the terminals 8 of the component 7 are mounted on the via window 5. As described above, since the via window 5 is formed in advance when a component is mounted, the mounting accuracy of the component becomes the alignment accuracy of the position of the hole of the via window 5 and the terminal 8, and thus high mounting accuracy can be realized. In addition, since the pattern and via window forming process is performed prior to the component mounting process, the pattern 4 that is likely to cause a defect is formed first, so that it is possible to suppress the unnecessary mounting of the component 7. In other words, since the circuit is formed first, it is possible to avoid component mounting at a circuit defective portion when the component 7 is mounted. Further, by setting the height of the via window 5 appropriately, the future depth of the via 9 can be determined to some extent.

次に、図４に示すように、積層工程を行う。この工程は、絶縁材料（例えばプリプレグ）からなる絶縁層１０を配し、さらに導体パターン４が形成された金属板１を重ねてプレスし、絶縁層１０内に部品７を埋設させる工程である。これにより、部品７は内蔵されることになる。   Next, as shown in FIG. 4, a lamination process is performed. This step is a step in which an insulating layer 10 made of an insulating material (for example, prepreg) is disposed, and the metal plate 1 on which the conductor pattern 4 is formed is stacked and pressed, and the component 7 is embedded in the insulating layer 10. As a result, the component 7 is built in.

次に、上記導体パターン４の一部として形成された部分を位置決めマーク１１として定め、この位置決めマーク１１が露出するようにリムーバ等を用いて金属板１の一部を除去する位置決めマーク露出工程を行ってもよい。これにより、次なるビア形成工程にて位置決めマーク１１を基準としてビア９を形成することができ、ビア形成の孔あけ位置精度の向上に寄与できる。また、この位置決めマーク１１は部品７搭載のための位置決めとしても利用できる。   Next, a positioning mark exposing step is performed in which a portion formed as a part of the conductor pattern 4 is defined as a positioning mark 11 and a part of the metal plate 1 is removed using a remover or the like so that the positioning mark 11 is exposed. You may go. As a result, the via 9 can be formed with the positioning mark 11 as a reference in the subsequent via formation step, which can contribute to improvement of the drilling position accuracy of the via formation. The positioning mark 11 can also be used for positioning for mounting the component 7.

このように、位置決めマーク露出工程を行う場合、上述したパターン及びビアウインド形成工程にて、導体パターン４とビアウインド５と位置決めマーク１１を同時に同じ精度で形成することになるので、ビア９と導体パターン４との位置ずれがなくなり、さらに位置決めマーク１１を介するので導体パターン４と部品７との位置精度も搭載機精度のみの問題となり、精度よくビア９を形成でき、基板全体としての制度も各段に向上する。位置決めマーク１１を部品７の搭載とビア９の孔あけ加工に用いることで、同一マークを用いた部品７とビア９との整合を図れるので、極めて位置精度の高い基板を得ることができる。   As described above, when the positioning mark exposing process is performed, the conductor pattern 4, the via window 5, and the positioning mark 11 are simultaneously formed with the same accuracy in the pattern and via window forming process described above. Since the positional deviation from the pattern 4 is eliminated and the positioning mark 11 is interposed, the positional accuracy between the conductor pattern 4 and the component 7 is only a problem of the mounting machine accuracy, the via 9 can be formed with high accuracy, and the system as a whole substrate Improve step by step. By using the positioning mark 11 for mounting the component 7 and drilling the via 9, the alignment between the component 7 and the via 9 using the same mark can be achieved, so that a substrate with extremely high positional accuracy can be obtained.

次に、図５に示すように、ビア形成工程を行う。この工程では、ビアウインド５を通って端子８まで到達するビア９を形成する。このビア９はレーザ加工によって形成されるが、ドリルを用いてもよい。このビア９は、上述したように位置決めマーク１１を露出した場合は当該マーク１１を基準に設けてもよいが、位置決めマーク露出工程を行わなかった場合は、Ｘ線等を用いてビアウインド５を検出して位置合わせをする。なお、ビア９の位置合わせとしては、上下の金属板１を貫通するスルーホール１２を設け、このスルーホール１２を基準として行ってもよい。さらには、図８に示すように、予めビアウインド露出工程を行い、金属板１の一部を除去して開口部１３を形成し、ビアウインド５を露出させてもよい。このようにビアウインド５を露出させれば、ビア９の孔あけの位置を視認することができるので、ビア９形成の孔あけ位置精度をさらに向上させることができる。ビアウインド露出工程と位置決めマーク露出工程を両方行い、さらにビア９の位置決め精度を高めてもよい。また、金属板１を薄くしておけば、ビア９の形成が容易となる。   Next, as shown in FIG. 5, a via formation process is performed. In this step, a via 9 that reaches the terminal 8 through the via window 5 is formed. The via 9 is formed by laser processing, but a drill may be used. The via 9 may be provided based on the mark 11 when the positioning mark 11 is exposed as described above. However, when the positioning mark exposure process is not performed, the via window 5 is formed using X-rays or the like. Detect and align. The alignment of the vias 9 may be performed using a through hole 12 penetrating the upper and lower metal plates 1 and using the through hole 12 as a reference. Further, as shown in FIG. 8, a via window exposure process may be performed in advance to remove a part of the metal plate 1 to form the opening 13 to expose the via window 5. If the via window 5 is exposed in this manner, the drilling position of the via 9 can be visually recognized, so that the drilling position accuracy in forming the via 9 can be further improved. Both the via window exposing step and the positioning mark exposing step may be performed to further increase the positioning accuracy of the via 9. If the metal plate 1 is made thin, the via 9 can be easily formed.

次に、図６に示すように、導通ビア形成工程を行う。この工程では、ビア９に対してめっき処理を施し、金属材料を充填して導通ビア１４を形成する。めっき処理に先立って、ビア９にはデスミア処理が施される。めっき金属は金属膜２と同じ銅が用いられる。すなわち、銅めっき処理が施される。スルーホール１２内にも銅めっきが施されるので、これにより両面の導通が図られる。めっき処理後、ビア９は銅めっきで充填され、外部との電気的接続のためにランド１５が形成される。このランド１５は同様にスルーホール１２に施されためっきにも形成される。めっき処理としては、基板の全面にめっきしてエッチングにてランド１５を形成してもよいし、ランド１５以外の部分をレジストしてめっき処理してもよい。   Next, as shown in FIG. 6, a conductive via forming step is performed. In this step, the via 9 is plated and filled with a metal material to form the conductive via 14. Prior to the plating process, the via 9 is subjected to a desmear process. The same copper as the metal film 2 is used for the plating metal. That is, a copper plating process is performed. Since copper plating is performed also in the through hole 12, this allows conduction on both sides. After the plating process, the via 9 is filled with copper plating, and a land 15 is formed for electrical connection with the outside. Similarly, the land 15 is formed on the plating applied to the through hole 12. As the plating treatment, the entire surface of the substrate may be plated and the land 15 may be formed by etching, or a portion other than the land 15 may be resisted and plated.

次に、図７に示すように、パターン露出工程を行う。この工程では、金属板１を除去して導体パターン４を露出させる。この除去はニッケル用のリムーバを用いて行われる。これにより、導体パターン４が露出して部品内蔵基板１６が製造される。   Next, as shown in FIG. 7, a pattern exposure process is performed. In this step, the metal plate 1 is removed and the conductor pattern 4 is exposed. This removal is performed using a nickel remover. Thereby, the conductor pattern 4 is exposed and the component built-in substrate 16 is manufactured.

１：金属板、２：金属膜、３：板体、４：導体パターン、５：ビアウインド、６：接着剤、７：部品、８：端子、９：ビア、１０：絶縁層、１１：位置決めマーク、１２：スルーホール、１３：開口部、１４：導通ビア、１５：ランド、１６：部品内蔵基板 1: Metal plate, 2: Metal film, 3: Plate body, 4: Conductor pattern, 5: Via window, 6: Adhesive, 7: Parts, 8: Terminal, 9: Via, 10: Insulating layer, 11: Positioning Mark: 12: Through hole, 13: Opening, 14: Conductive via, 15: Land, 16: Component built-in board

Claims (3)

金属板の表面に前記金属板に用いられた金属材料とは異なる導電金属材料を用いて導体パターン及びビアの一部分となるべきビアウインドを形成するパターン及びビアウインド形成工程と、
前記ビアウインドを覆うように接着剤を塗布し、該接着剤を介して前記ビアウインド上に端子を配して電気又は電子的な部品を搭載する部品搭載工程と、
前記ビアウインドを通って前記端子まで到達するビアを形成するビア形成工程と、
前記ビアに対してめっき処理を施し、金属材料を充填して導通ビアとする導通ビア形成工程と、
前記金属板を除去して前記導体パターンを露出させるパターン露出工程とを備えたことを特徴とする部品内蔵基板の製造方法。A pattern and via window forming step for forming a conductor pattern and a via window to be a part of a via using a conductive metal material different from the metal material used for the metal plate on the surface of the metal plate;
Applying an adhesive so as to cover the via window, arranging a terminal on the via window via the adhesive and mounting an electrical or electronic component; and
A via formation step of forming a via reaching the terminal through the via window;
Conductive via forming step of plating the via and filling the metal material into a conductive via;
And a pattern exposing step of exposing the conductor pattern by removing the metal plate. 前記ビア形成工程の前に、前記金属板の一部を除去して前記ビアウインドを露出させるビアウインド露出工程を備えたことを特徴とする請求項１に記載の部品内蔵基板の製造方法。   2. The method of manufacturing a component-embedded board according to claim 1, further comprising a via window exposing step of exposing the via window by removing a part of the metal plate before the via forming step. 前記ビア形成工程の前に、予め位置決めマークとして定めた前記導体パターンの一部を露出させるために前記金属板の一部を除去する位置決めマーク露出工程を備え、
前記ビア形成工程にて、前記位置決めマークを基準として前記ビアを形成することを特徴とする請求項１に記載の部品内蔵基板の製造方法。Before the via forming step, a positioning mark exposing step of removing a part of the metal plate in order to expose a part of the conductor pattern previously determined as a positioning mark,
The method for manufacturing a component-embedded substrate according to claim 1, wherein the via is formed in the via forming step with reference to the positioning mark.
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