JPWO2012115267A1 - Photoelectric conversion element and photoelectric conversion device - Google Patents
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 98
- 239000004065 semiconductor Substances 0.000 claims abstract description 136
- 230000031700 light absorption Effects 0.000 claims abstract description 77
- 150000001875 compounds Chemical class 0.000 claims abstract description 13
- 239000011148 porous material Substances 0.000 claims abstract description 12
- 229910052717 sulfur Inorganic materials 0.000 claims description 12
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 11
- 239000011593 sulfur Substances 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 239000011800 void material Substances 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 3
- 230000032683 aging Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 272
- 239000000243 solution Substances 0.000 description 35
- 238000000034 method Methods 0.000 description 30
- 239000002245 particle Substances 0.000 description 28
- 238000004544 sputter deposition Methods 0.000 description 25
- 239000010408 film Substances 0.000 description 24
- 238000004519 manufacturing process Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 16
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 239000013078 crystal Substances 0.000 description 10
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 239000011787 zinc oxide Substances 0.000 description 8
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 230000005587 bubbling Effects 0.000 description 6
- 229910052798 chalcogen Inorganic materials 0.000 description 6
- 229910003437 indium oxide Inorganic materials 0.000 description 6
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 6
- 150000001787 chalcogens Chemical class 0.000 description 5
- 238000001035 drying Methods 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 229910052711 selenium Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 150000002894 organic compounds Chemical class 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- DVRDHUBQLOKMHZ-UHFFFAOYSA-N chalcopyrite Chemical compound [S-2].[S-2].[Fe+2].[Cu+2] DVRDHUBQLOKMHZ-UHFFFAOYSA-N 0.000 description 2
- 229910052951 chalcopyrite Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000012046 mixed solvent Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052795 boron group element Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002149 energy-dispersive X-ray emission spectroscopy Methods 0.000 description 1
- 239000005357 flat glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 150000003958 selenols Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 125000004434 sulfur atom Chemical group 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- TULWUZJYDBGXMY-UHFFFAOYSA-N tellurophene Chemical compound [Te]1C=CC=C1 TULWUZJYDBGXMY-UHFFFAOYSA-N 0.000 description 1
- 150000003573 thiols Chemical class 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
- H01L31/022475—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers composed of indium tin oxide [ITO]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/035281—Shape of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0749—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CulnSe2 [CIS] heterojunction solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/541—CuInSe2 material PV cells
Abstract
【課題】透明電極に存在する多数の電子が、光吸収層のホールに近いと、経年変化でｐｎ接合界面での欠陥が増加する場合があった。【解決手段】下部電極層と、この下部電極層上に設けられた、光電変換可能な化合物半導体を含む光吸収層と、この光吸収層上に設けられた半導体層と、この半導体層上に設けられた、この半導体層よりも抵抗率が低い上部電極層とを有する光電変換素子であって、前記半導体層は、前記上部電極層側に、多数の空孔を有する多孔質層領域を有する。When a large number of electrons existing in a transparent electrode are close to holes in a light absorption layer, defects at a pn junction interface may increase due to aging. A lower electrode layer, a light absorption layer including a compound semiconductor capable of photoelectric conversion provided on the lower electrode layer, a semiconductor layer provided on the light absorption layer, and on the semiconductor layer A photoelectric conversion element having an upper electrode layer having a lower resistivity than the semiconductor layer, wherein the semiconductor layer has a porous layer region having a large number of pores on the upper electrode layer side; .
Description
本発明は光電変換素子および光電変換装置に関する。 The present invention relates to a photoelectric conversion element and a photoelectric conversion device.
太陽光発電などに使用される光電変換装置としては、光吸収係数が高いＣＩＧＳなどのカルコパイライト系のＩ−III−VI族化合物半導体によって光吸収層が形成されたものがある。ＣＩＧＳは光吸収係数が高く、光電変換装置の薄膜化や大面積化や低コスト化に適しており、これを用いた次世代太陽電池の研究開発が進められている。 As a photoelectric conversion device used for solar power generation or the like, there is one in which a light absorption layer is formed of a chalcopyrite-based I-III-VI group compound semiconductor such as CIGS having a high light absorption coefficient. CIGS has a high light absorption coefficient and is suitable for reducing the thickness, area, and cost of photoelectric conversion devices, and research and development of next-generation solar cells using the photoelectric conversion device is being promoted.
その光電変換素子は、ガラスなどの基板上に、金属電極などの下部電極と、光吸収層やバッファ層などを含む半導体層である光電変換層と、透明電極や金属電極などの上部電極とが、この順に積層されて構成される。そして、複数の光電変換素子は、隣り合う一方の光電変換素子の上部電極と他方の光電変換素子の下部電極とが、接続導体によって電気的に接続されることで、電気的に直列に接続されている。 The photoelectric conversion element includes a lower electrode such as a metal electrode on a substrate such as glass, a photoelectric conversion layer that is a semiconductor layer including a light absorption layer and a buffer layer, and an upper electrode such as a transparent electrode and a metal electrode. These are stacked in this order. The plurality of photoelectric conversion elements are electrically connected in series by electrically connecting the upper electrode of one adjacent photoelectric conversion element and the lower electrode of the other photoelectric conversion element by a connecting conductor. ing.
このような光電変換素子は、例えば、光吸収層上に化学析出法によりＣｄＳを厚さ１０ｎｍに析出させて、バッファ層を形成し、このバッファ層上にＺｎＯターゲットとＭｇＯターゲットの二元ターゲットを用いたスパッタリング法により、Ｚｎ０．８５Ｍｇ０．１５Ｏから成る１．２μｍの膜厚の上部電極層を形成することによって作製されることが知られている（例えば特許文献１参照）。In such a photoelectric conversion element, for example, CdS is deposited on a light absorption layer by a chemical deposition method to a thickness of 10 nm to form a buffer layer, and a binary target of a ZnO target and an MgO target is formed on the buffer layer. It is known that the upper electrode layer made of Zn 0.85 Mg 0.15 O and having a thickness of 1.2 μm is formed by the sputtering method used (see, for example, Patent Document 1).
しかしながら、特許文献１に開示された光電変換素子では、光吸収層等へスパッタリング粒子が打ち込まれることによってダメージを受け、光電変換効率を十分に高めることが困難であった。 However, the photoelectric conversion element disclosed in Patent Document 1 is damaged by sputtered particles being implanted into the light absorption layer and the like, and it has been difficult to sufficiently increase the photoelectric conversion efficiency.
また、透明電極に存在する多数の電子が、光吸収層のホールに近いと、電子とホールが再結合し易くなる傾向があり、光電変換効率を十分に高めることが困難であった。 Further, when a large number of electrons existing in the transparent electrode are close to the holes of the light absorption layer, the electrons and the holes tend to recombine, and it is difficult to sufficiently increase the photoelectric conversion efficiency.
よって本発明は、光電変換素子および光電変換装置の光電変換効率を高めることを目的とする。 Therefore, an object of this invention is to improve the photoelectric conversion efficiency of a photoelectric conversion element and a photoelectric conversion apparatus.
上記に鑑みて本発明の一実施形態に係る光電変換素子は、下部電極層と、該下部電極層上に設けられた、光電変換可能な化合物半導体を含む光吸収層と、該光吸収層上に設けられた半導体層と、該半導体層上に設けられた、該半導体層よりも抵抗率が低い上部電極層とを有する光電変換素子であって、前記半導体層は、前記上部電極層側に、多数の空孔を有する多孔質層領域を有する。 In view of the above, a photoelectric conversion element according to an embodiment of the present invention includes a lower electrode layer, a light absorption layer including a photoelectrically convertible compound semiconductor provided on the lower electrode layer, and the light absorption layer. A photoelectric conversion element having a semiconductor layer provided on the semiconductor layer and an upper electrode layer having a lower resistivity than the semiconductor layer provided on the semiconductor layer, wherein the semiconductor layer is disposed on the upper electrode layer side. A porous layer region having a large number of pores.
また、本発明の他の一実施形態に係る光電変換素子は、下部電極層と、該下部電極層上に設けられた、光電変換可能な化合物半導体を含む光吸収層と、該光吸収層上に設けられた第１半導体層と、該第１半導体層上に設けられた第２半導体層と、該第２半導体層上に設けられた、該第２半導体層よりも抵抗率が低い上部電極層とを有する光電変換素子であって、前記第１半導体層は、前記第２半導体層側に、多数の空孔を有する第１多孔質層領域を有する。 In addition, a photoelectric conversion element according to another embodiment of the present invention includes a lower electrode layer, a light absorption layer including a compound semiconductor capable of photoelectric conversion provided on the lower electrode layer, and the light absorption layer. A first semiconductor layer provided on the first semiconductor layer; a second semiconductor layer provided on the first semiconductor layer; and an upper electrode provided on the second semiconductor layer and having a lower resistivity than the second semiconductor layer. The first semiconductor layer has a first porous layer region having a large number of pores on the second semiconductor layer side.
また、本発明の他の一実施形態に係る光電変換装置は、前記光電変換素子を用いたものである。 Moreover, the photoelectric conversion apparatus which concerns on other one Embodiment of this invention uses the said photoelectric conversion element.
本発明の光電変換素子および光電変換装置によれば、光吸収層等へスパッタリング粒子が打ち込まれることによるダメージを低減し、光電変換効率を高めることができる。 According to the photoelectric conversion element and the photoelectric conversion device of the present invention, it is possible to reduce damage caused by the sputtered particles being implanted into the light absorption layer and the like and increase the photoelectric conversion efficiency.
また、上部電極に存在する多数の電子を、半導体層に空孔を有する分だけ、光吸収層のホールから遠ざけることができるので、電子とホールとの再結合を低減して光電変換効率を高めることができる。 In addition, since a large number of electrons existing in the upper electrode can be moved away from the holes in the light absorption layer by the amount of holes in the semiconductor layer, the recombination of electrons and holes is reduced to increase the photoelectric conversion efficiency. be able to.
以下、本発明の一実施形態を図面に基づいて説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
＜第１実施形態に係る光電変換素子＞
図２において光電変換素子１は、基板２上に下部電極層３と、光吸収層４と、半導体層５と、上部電極層７と、グリッド電極８とを主として備えている。<Photoelectric Conversion Element According to First Embodiment>
In FIG. 2, the photoelectric conversion element 1 mainly includes a lower electrode layer 3, a light absorption layer 4, a semiconductor layer 5, an upper electrode layer 7, and a grid electrode 8 on a substrate 2.
基板２に用いられる材料としては、ガラス、セラミックス、樹脂および金属などが挙げられる。ここでは、基板２として、厚さ１〜３ｍｍ程度の青板ガラス（ソーダライムガラス）が用いられている。 Examples of the material used for the substrate 2 include glass, ceramics, resin, and metal. Here, a blue plate glass (soda lime glass) having a thickness of about 1 to 3 mm is used as the substrate 2.
下部電極層３は、基板２の一主面上に設けられた、Ｍｏ、Ａｌ、Ｔｉ、ＴａまたはＡｕなどの金属、あるいはこれらの金属の積層構造体からなる導体である。下部電極層２は、スパッタリング法または蒸着法などの公知の薄膜形成方法を用いて、０．２〜１μｍ程度の厚みに形成される。 The lower electrode layer 3 is a conductor made of a metal such as Mo, Al, Ti, Ta or Au, or a laminated structure of these metals provided on one main surface of the substrate 2. The lower electrode layer 2 is formed to a thickness of about 0.2 to 1 μm using a known thin film forming method such as a sputtering method or a vapor deposition method.
光吸収層４は、下部電極層３の上に設けられた、例えばカルコパイライト系（以下ＣＩＳ系とも言う）のＩ−III−VI族化合物を含む、ｐ型の導電型を有する半導体層であることが好ましい。この光吸収層４は、１〜３μｍ程度の厚みを有している。ここで、Ｉ−III−VI族化合物とは、Ｉ−Ｂ族元素と、III−Ｂ族元素とVI−Ｂ族元素（換言すれば、１１族元素、１３族元素、１６族元素ともいう）との化合物であり、本実施形態としては、Ｃｕ（Ｉｎ、Ｇａ）Ｓｅ２（以下、ＣＩＧＳとも言う）などが挙げられるが、これらに限定されるものではない。このような光吸収層４については、スパッタリング法、蒸着法などのいわゆる真空プロセスによって形成可能であるほか、光吸収層４の構成元素を含む溶液を下部電極層３の上に塗布し、その後、乾燥・熱処理を行う、いわゆる塗布法あるいは印刷法と称されるプロセスによって形成することもできる。The light absorption layer 4 is a semiconductor layer having a p-type conductivity type, for example, containing a chalcopyrite-based (hereinafter also referred to as CIS-based) I-III-VI group compound provided on the lower electrode layer 3. It is preferable. The light absorption layer 4 has a thickness of about 1 to 3 μm. Here, the I-III-VI group compound is a group IB element, a group III-B element and a group VI-B element (in other words, also referred to as a group 11 element, a group 13 element, or a group 16 element). In this embodiment, Cu (In, Ga) Se 2 (hereinafter also referred to as CIGS) and the like are exemplified, but the present invention is not limited thereto. Such a light absorbing layer 4 can be formed by a so-called vacuum process such as a sputtering method or a vapor deposition method, and a solution containing the constituent elements of the light absorbing layer 4 is applied on the lower electrode layer 3, and then It can also be formed by a so-called coating method or printing method in which drying and heat treatment are performed.
半導体層５は、光吸収層４の上に設けられた、該光吸収層４の導電型とは異なるｎ型の導電型を有する半導体層である。半導体層５は光吸収層４上に設けられたII−Ｂ族元素、III−Ｂ族元素の少なくとも１つを含む化合物半導体を有する半導体層によって構成される場合に、光吸収層４とヘテロ接合する態様で設けられる。光電変換素子１では、このヘテロ接合を構成する光吸収層４と半導体層５とにおいて光電変換が生じることから、光吸収層４と半導体層５とが光電変換層となっている。また、半導体層５はＣＢＤ法（ケミカルバス成膜法）によって、例えば、Ｉｎ２Ｓ３系、ＺｎＳ系、ＣｄＳ系等の組成で構成され、１〜３０ｎｍの厚みに形成されることが好ましいが、可能であれば薄膜法、メッキ法などの他の手段によって形成されても構わない。The semiconductor layer 5 is a semiconductor layer provided on the light absorption layer 4 and having an n-type conductivity type different from the conductivity type of the light absorption layer 4. When the semiconductor layer 5 is formed of a semiconductor layer having a compound semiconductor containing at least one of a group II-B element and a group III-B element provided on the light absorption layer 4, a heterojunction with the light absorption layer 4 It is provided in the mode to do. In the photoelectric conversion element 1, since photoelectric conversion occurs in the light absorption layer 4 and the semiconductor layer 5 constituting the heterojunction, the light absorption layer 4 and the semiconductor layer 5 are photoelectric conversion layers. In addition, the semiconductor layer 5 is preferably formed by a CBD method (chemical bath film formation method), for example, with a composition of In 2 S 3 system, ZnS system, CdS system, etc., and with a thickness of 1 to 30 nm. If possible, it may be formed by other means such as a thin film method or a plating method.
上部電極層７は、半導体層５の上に設けられた、ｎ型の導電型を有する透明導電膜である。上部電極層７は、光電変換層において生じた電荷を取り出す電極として設けられている。また、上部電極層７は、半導体層５よりも低い抵抗率を有する物質、例えば錫を含んだ酸化インジウム（ＩＴＯ）などによって構成されるものであり、上部電極層７は、スパッタリング法、蒸着法などによって形成される。 The upper electrode layer 7 is a transparent conductive film having an n-type conductivity provided on the semiconductor layer 5. The upper electrode layer 7 is provided as an electrode for extracting charges generated in the photoelectric conversion layer. The upper electrode layer 7 is made of a material having a resistivity lower than that of the semiconductor layer 5, such as indium oxide (ITO) containing tin, and the upper electrode layer 7 is formed by sputtering or vapor deposition. Formed by.
なお、半導体層５、上部電極層７は、光吸収層４が吸収する光の波長領域に対して光透過性を有する物質によって構成されることが好ましく、また、半導体層５、上部電極層７は、絶対屈折率が略同一であることが好ましい。これにより、光吸収層４までの光の吸収効率の低下が抑制される。 Note that the semiconductor layer 5 and the upper electrode layer 7 are preferably made of a material having light transmittance with respect to the wavelength region of the light absorbed by the light absorption layer 4, and the semiconductor layer 5 and the upper electrode layer 7. Are preferably substantially the same in absolute refractive index. Thereby, the fall of the light absorption efficiency to the light absorption layer 4 is suppressed.
そして、図１に示されるような、Ａｇなどの金属からなる集電部８ａと連結部８ｂとからなるグリッド電極８は、光電変換素子１において発生した電荷を上部電極層７から取り出して集電する役割を担うものであり、これにより上部電極層７の薄層化が可能となる。グリッド電極８は、導電性と、光吸収層４への光透過性との両立を考慮すると、５０〜４００μｍの幅を有することが好ましい。 As shown in FIG. 1, the grid electrode 8 including the current collector 8 a made of a metal such as Ag and the connecting portion 8 b takes out the electric charge generated in the photoelectric conversion element 1 from the upper electrode layer 7 and collects the current. Thus, the upper electrode layer 7 can be thinned. The grid electrode 8 preferably has a width of 50 to 400 μm in consideration of both conductivity and light transmittance to the light absorption layer 4.
上記半導体層５について詳細に説明する。 The semiconductor layer 5 will be described in detail.
第１実施形態において、半導体層５は、上部電極層７側に、多数の空孔を有する多孔質層領域を有する。 In the first embodiment, the semiconductor layer 5 has a porous layer region having a large number of pores on the upper electrode layer 7 side.
例えば、図６および図７に示されるように、光吸収層４と、光吸収層４上に設けられた半導体層５と、半導体層５上に設けられた上部電極層７とを有しており、半導体層５は、上部電極層７側に、多数の空孔５ｂを有する多孔質層領域５ａを有する。 For example, as shown in FIGS. 6 and 7, the light absorption layer 4, the semiconductor layer 5 provided on the light absorption layer 4, and the upper electrode layer 7 provided on the semiconductor layer 5 are provided. The semiconductor layer 5 has a porous layer region 5a having a large number of holes 5b on the upper electrode layer 7 side.
これによって、上部電極７に存在する多数の電子を、半導体層５に空孔５ｂを有する分だけ、光吸収層４のホールから遠ざけることができるので、電子とホールとの再結合を低減して光電変換効率を高めることができる。 As a result, a large number of electrons existing in the upper electrode 7 can be moved away from the holes of the light absorption layer 4 by the amount of the holes 5b in the semiconductor layer 5, thereby reducing recombination of electrons and holes. Photoelectric conversion efficiency can be increased.
さらに、上部電極層７をスパッタリング法で形成する際に、スパッタリング粒子のピンニング（打ち込み）を空孔５ｂでトラップして防いで、光吸収層４へのダメージを低減することができる。 Furthermore, when the upper electrode layer 7 is formed by the sputtering method, the pinning (injection) of the sputtered particles is trapped and prevented by the holes 5b, and damage to the light absorption layer 4 can be reduced.
ここで多孔質層領域５ａとは、半導体層５で囲まれた空孔５ｂが多数存在する層領域であること、すなわち閉気孔である空孔５ｂが多数、上部電極層７側に分布していることが、ピンニングされたスパッタリング粒子を捕捉し易い点で好ましい。 Here, the porous layer region 5a is a layer region in which a large number of holes 5b surrounded by the semiconductor layer 5 exist, that is, a large number of closed holes 5b are distributed on the upper electrode layer 7 side. It is preferable that pinned sputtered particles are easily captured.
またここで、多孔質層領域５ａの空孔５ｂとは、例えば、図８および図９のＴＥＭ分析写真において、黒く見える部分である。 Here, the pores 5b in the porous layer region 5a are, for example, portions that appear black in the TEM analysis photographs of FIGS.
本実施形態では、半導体層５は硫黄元素および酸素元素を含み、半導体層５に含まれる硫黄元素の原子％をＳ、酸素元素の原子％をＯとしたとき、Ｓ／（Ｓ＋Ｏ）が光吸収層４側ほど大きいことが好ましい。 In the present embodiment, the semiconductor layer 5 contains sulfur element and oxygen element, and S / (S + O) absorbs light when the atomic% of the sulfur element contained in the semiconductor layer 5 is S and the atomic% of the oxygen element is O. It is preferable that the layer 4 side is larger.
さらに、多孔質層領域５ａにおいて、Ｓ／（Ｓ＋Ｏ）が０．６〜０．７９であることが好ましい。 Furthermore, in the porous layer region 5a, S / (S + O) is preferably 0.6 to 0.79.
各原子％は半導体層５の各部位においてＴＥＭのＥＤＳ分析で測定可能であり、半導体層５における光吸収層４との界面付近において、この範囲を満足することが好ましい。 Each atomic% can be measured at each part of the semiconductor layer 5 by TEM EDS analysis, and it is preferable that this range be satisfied in the vicinity of the interface of the semiconductor layer 5 with the light absorption layer 4.
これにより、ｐｎ接合付近では酸素を少なく、硫黄を多くできるので、ｐｎ接合を良好に保つことができる。 Thereby, since oxygen can be reduced and sulfur can be increased in the vicinity of the pn junction, the pn junction can be maintained well.
本実施形態は、光吸収層がＩ−Ｂ族元素、III−Ｂ族元素およびVI−Ｂ族元素を含み、半導体層がIII−Ｂ族元素およびVI−Ｂ族元素を含む。 In the present embodiment, the light absorption layer includes a group IB element, a group III-B element, and a group VI-B element, and the semiconductor layer includes a group III-B element and a group VI-B element.
これにより、上部電極層７のスパッタリング粒子が光吸収層４へダメージを与えることを低減することができる。 Thereby, it can reduce that the sputtered particle of the upper electrode layer 7 damages the light absorption layer 4.
本実施形態では、多孔質層領域５ａにおける空孔率は、面積比で１０〜８０％であることが好ましい。 In the present embodiment, the porosity in the porous layer region 5a is preferably 10 to 80% in terms of area ratio.
これにより、半導体層５の多孔質領域５ａと上部電極層７との密着性を維持しつつ、上部電極層７をスパッタリング法で形成する際に、スパッタリング粒子のピンニング（打ち込み）を空孔５ｂでトラップして防いで、光吸収層４へのダメージを低減することができる。 Accordingly, when the upper electrode layer 7 is formed by the sputtering method while maintaining the adhesion between the porous region 5a of the semiconductor layer 5 and the upper electrode layer 7, the sputtering particles are pinned (injected) by the holes 5b. By trapping and preventing, damage to the light absorption layer 4 can be reduced.
ここで空孔率は、多孔質領域５ａにおける空孔５ｂと、空孔５ｂが無い部分とに、画像処理解析装置を使用して２値化処理し、それぞれの面積を測定、演算することによって求めることができる。 Here, the porosity is obtained by binarizing the pore 5b in the porous region 5a and the portion without the pore 5b using an image processing analyzer, and measuring and calculating the respective areas. Can be sought.
また、上部電極層７に存在する多数の電子を、半導体層５に空孔５ｂを有する分だけ、光吸収層４のホールから遠ざけることができるので、光電変換効率を高めることができる。 In addition, since a large number of electrons existing in the upper electrode layer 7 can be moved away from the holes of the light absorption layer 4 by the amount of the holes 5b in the semiconductor layer 5, the photoelectric conversion efficiency can be increased.
＜第２実施形態に係る光電変換素子＞
第２実施形態において、図１０に示すように、下部電極層１３と、下部電極層１３上に設けられた、光電変換可能な化合物半導体を含む光吸収層１４と、光吸収層１４上に設けられた第１半導体層１５と、第１半導体層１５上に設けられた第２半導体層１６と、第２半導体層１６上に設けられた、第２半導体層１６よりも抵抗率が低い上部電極層１７とを有する光電変換素子１１であって、第１半導体層１５は、第２半導体層１６側に、多数の空孔１５ｂを有する第１多孔質層領域１５ａを有する。<Photoelectric Conversion Element According to Second Embodiment>
In the second embodiment, as shown in FIG. 10, the lower electrode layer 13, the light absorption layer 14 including a compound semiconductor capable of photoelectric conversion provided on the lower electrode layer 13, and the light absorption layer 14 are provided. The first semiconductor layer 15 formed, the second semiconductor layer 16 provided on the first semiconductor layer 15, and the upper electrode provided on the second semiconductor layer 16 and having a lower resistivity than the second semiconductor layer 16 The first semiconductor layer 15 includes a first porous layer region 15a having a large number of pores 15b on the second semiconductor layer 16 side.
すなわち、図１７、図１８に示されるように、光吸収層１４と、光吸収層１４上に設けられた第１半導体層１５と、第１半導体層１５上に設けられた第２半導体層１６とを有しており、第１半導体層５１は、第２半導体層１６側に、多数の空孔１５ｂを有する第１多孔質層領域１５ａを有する。 That is, as shown in FIGS. 17 and 18, the light absorption layer 14, the first semiconductor layer 15 provided on the light absorption layer 14, and the second semiconductor layer 16 provided on the first semiconductor layer 15. The first semiconductor layer 51 has a first porous layer region 15a having a large number of holes 15b on the second semiconductor layer 16 side.
これによって、上部電極層１７に存在する多数の電子を、第１半導体層１５に空孔１５ｂを有する分だけ、光吸収層１４のホールから遠ざけることができるので、電子とホールとの再結合を低減して光電変換効率を高めることができる。 As a result, a large number of electrons existing in the upper electrode layer 17 can be moved away from the holes of the light absorption layer 14 by the amount of the holes 15b in the first semiconductor layer 15, so that recombination of electrons and holes can be performed. This can reduce the photoelectric conversion efficiency.
さらに、第２半導体層１６をスパッタリング法で形成する際に、スパッタリング粒子のピンニング（打ち込み）を空孔１５ｂでトラップして防いで、光吸収層１４へのダメージを低減することができる。ここで第１多孔質層領域１５ａは、第１半導体層１５で囲まれた空孔１５ｂが多数存在する層領域であること、すなわち閉気孔である空孔５ｂが多数、第２半導体層１６側に分布していることが、ピンニングされたスパッタリング粒子を捕捉し易い点で好ましい。 Furthermore, when the second semiconductor layer 16 is formed by the sputtering method, the pinning (implantation) of the sputtered particles can be trapped and prevented by the holes 15b, and damage to the light absorption layer 14 can be reduced. Here, the first porous layer region 15a is a layer region in which a large number of holes 15b surrounded by the first semiconductor layer 15 are present, that is, a large number of closed holes 5b are present on the second semiconductor layer 16 side. It is preferable that the pinned sputtered particles are easily captured.
さらに、本実施形態は、第１半導体層１５は硫黄元素および酸素元素を含み、第１半導体層１５に含まれる硫黄元素の原子％をＳ、酸素元素の原子％をＯとしたとき、Ｓ／（Ｓ＋Ｏ）が光吸収層側ほど大きい構成であることが好ましい。 Further, in the present embodiment, when the first semiconductor layer 15 contains a sulfur element and an oxygen element, S / is the atomic% of the sulfur element contained in the first semiconductor layer 15 and O is the atomic% of the oxygen element. It is preferable that (S + O) is configured to be larger toward the light absorption layer side.
さらに、多孔質層領域１５ａにおいて、Ｓ／（Ｓ＋Ｏ）が０．５〜０．６９であることが好ましい。 Furthermore, in the porous layer region 15a, S / (S + O) is preferably 0.5 to 0.69.
これにより、ｐｎ接合付近では酸素を少なく、硫黄を多くできるので、ｐｎ接合を良好に保つことができる。 Thereby, since oxygen can be reduced and sulfur can be increased in the vicinity of the pn junction, the pn junction can be maintained well.
さらに、本実施形態は、光吸収層１４がＩ−Ｂ族元素、III−Ｂ族元素およびVI−Ｂ族元素を含み、第１半導体層１５がIII−Ｂ族元素およびVI−Ｂ族元素を含み、第２半導体層１６がII−Ｂ族元素およびVI−Ｂ族元素を含んでもよい。 Furthermore, in the present embodiment, the light absorption layer 14 includes a group IB element, a group III-B element, and a group VI-B element, and the first semiconductor layer 15 includes a group III-B element and a group VI-B element. In addition, the second semiconductor layer 16 may include a II-B group element and a VI-B group element.
より好ましくは、第１半導体層１５はＩｎ２Ｓ３を含み、第２半導体層１６はＺｎＯを含む。More preferably, the first semiconductor layer 15 includes In 2 S 3 and the second semiconductor layer 16 includes ZnO.
これにより、第２半導体層１６の例えばＺｎＯのスパッタリング粒子が光吸収層１４へダメージを与えることを低減することができ、さらに、ＺｎＯのＺｎが第１半導体層１５を介して光吸収層１４に経年変化によって拡散していき、ｐｎ接合を良好に行うことができる。 Thereby, it is possible to reduce, for example, ZnO sputtered particles of the second semiconductor layer 16 from damaging the light absorption layer 14, and ZnO Zn in the light absorption layer 14 via the first semiconductor layer 15. The pn junction can be satisfactorily performed by diffusing with aging.
さらに、本実施形態は、多孔質領域１５ａにおける空孔率は、面積比で１０〜８０％であることが好ましい。 Furthermore, in this embodiment, the porosity in the porous region 15a is preferably 10 to 80% in terms of area ratio.
これによって、上部電極層１７に存在する多数の電子を、半導体層１５に空孔１５ｂを有する分だけ、光吸収層１４のホールから遠ざけることができるので、電子とホールとの再結合をより低減して、光電変換効率を高めることができる。 As a result, a large number of electrons existing in the upper electrode layer 17 can be moved away from the holes of the light absorption layer 14 by the amount of the holes 15b in the semiconductor layer 15, thereby further reducing recombination of electrons and holes. Thus, the photoelectric conversion efficiency can be increased.
ここで空孔率は、多孔質領域１５ａにおける空孔１５ｂと、空孔１５ｂが無い部分とに、画像処理解析装置を使用して２値化処理し、それぞれの面積を測定、演算することによって求めることができる。 Here, the porosity is obtained by binarizing the pore 15b in the porous region 15a and the portion without the pore 15b using an image processing analyzer, and measuring and calculating the respective areas. Can be sought.
さらに、第２半導体層１６をスパッタリング法で形成する際に、スパッタリング粒子のピンニング（打ち込み）を空孔１５ｂでトラップして防いで、光吸収層１４へのダメージをより低減することができる。 Furthermore, when the second semiconductor layer 16 is formed by the sputtering method, pinning (implantation) of the sputtered particles can be trapped and prevented by the holes 15b, and damage to the light absorption layer 14 can be further reduced.
さらに、本実施形態は、多孔質層領域１５ａの厚さが５〜７０ｎｍである。 Furthermore, in this embodiment, the thickness of the porous layer region 15a is 5 to 70 nm.
空孔１５ｂにより、上部電極層１７および第２半導体層１６に存在する多数の電子を、光吸収層１４と第１半導体層１５とのｐｎ接合付近に存在するｐ型層のホールから遠ざけておくことが容易にできる。 A large number of electrons existing in the upper electrode layer 17 and the second semiconductor layer 16 are kept away from the holes of the p-type layer existing in the vicinity of the pn junction between the light absorption layer 14 and the first semiconductor layer 15 by the holes 15b. Can be easily done.
また、第２半導体層１６をスパッタリング法で形成する際に、スパッタリング粒子のピンニング（打ち込み）を空孔１５ｂで捕捉して、光吸収層１４へのダメージを適切に低減することができる。 Further, when the second semiconductor layer 16 is formed by the sputtering method, pinning (implantation) of the sputtered particles can be captured by the holes 15b, and damage to the light absorption layer 14 can be appropriately reduced.
＜光電変換装置＞
本実施形態は、光電変換素子を用いた光電変換装置を提供するものである。<Photoelectric conversion device>
The present embodiment provides a photoelectric conversion device using a photoelectric conversion element.
図１に示す例のように、光電変換装置１０は、上部電極層７、１７およびグリッド電極８（８ａは集電部、８ｂは接続部）が設けられた側の主面が受光面側となっており、それぞれの光電変換素子１、１１が直列あるいは並列接続されて光電変換装置１０となっている。 As in the example shown in FIG. 1, the photoelectric conversion device 10 includes a main surface on the side where the upper electrode layers 7 and 17 and the grid electrode 8 (8a is a current collecting portion and 8b is a connecting portion) are provided. The photoelectric conversion elements 1 and 11 are connected in series or in parallel to form a photoelectric conversion device 10.
上記した光電変換素子１、１１を光電変換装置１０に用いて、さらに高い光電変換効率を提供することが容易になる。 Using the photoelectric conversion elements 1 and 11 described above for the photoelectric conversion device 10 makes it easier to provide higher photoelectric conversion efficiency.
なお、本発明の光電変換装置１０は上記のような一実施形態に限られたものではない。 The photoelectric conversion device 10 of the present invention is not limited to the above-described embodiment.
＜光電変換素子の製造方法＞
以下において、光電変換素子の第１実施形態の製造方法、および第２実施形態の製造方法の説明をそれぞれ説明する。<Method for producing photoelectric conversion element>
In the following, the manufacturing method of the first embodiment of the photoelectric conversion element and the manufacturing method of the second embodiment will be described.
（第１実施形態の光電変換素子の製造方法）
Ｉ−III−VI族化合物半導体からなる光吸収層４（例えば、Ｃｕ、Ｉｎ、ＧａおよびＳｅを含むＣＩＧＳ等）が塗布法を用いて形成され、さらに、半導体層５以降が形成される場合を例として説明する。(Method for Manufacturing Photoelectric Conversion Element of First Embodiment)
A case where the light absorption layer 4 (for example, CIGS containing Cu, In, Ga, and Se) made of an I-III-VI group compound semiconductor is formed using a coating method, and the semiconductor layer 5 and subsequent layers are formed. This will be described as an example.
まず、図３のように、洗浄された基板２の略全面に、Ｍｏからなる下部電極層３がスパッタリング法で形成され、下部電極層３上にＩ−III−VI族化合物半導体からなる光吸収層４（例えば、Ｃｕ、Ｉｎ、ＧａおよびＳｅを含むＣＩＧＳ等）が塗布法を用いて形成される。 First, as shown in FIG. 3, a lower electrode layer 3 made of Mo is formed on substantially the entire surface of the cleaned substrate 2 by sputtering, and light absorption made of an I-III-VI group compound semiconductor is formed on the lower electrode layer 3. The layer 4 (for example, CIGS including Cu, In, Ga, and Se) is formed using a coating method.
ここで、光吸収層４を形成するための溶液が下部電極層３の表面に塗布され、乾燥によって被膜が形成された後、この被膜が熱処理されることで、光吸収層４が形成される。光吸収層４を形成するための溶液は、カルコゲン元素含有機化合物と塩基性有機溶剤とを含む溶媒に、Ｉ−Ｂ族金属およびIII−Ｂ族金属を直接溶解することで作製され、Ｉ−Ｂ族金属およびIII−Ｂ族金属の合計濃度が１０質量％以上の溶液とされる。なお、溶液の塗布にはスピンコーター、スクリーン印刷、ディッピング、スプレー、ダイコーターなど様々な方法の適用が可能である。カルコゲン元素含有有機化合物とは、カルコゲン元素を含む有機化合物である。カルコゲン元素としては、VI−Ｂ族元素のうちのＳ、Ｓｅ、Ｔｅをいう。カルコゲン元素含有有機化合物としては、例えば、チオール、スルフィド、セレノール、テルロール等が挙げられる。金属を混合溶媒に直接溶解させるというのは、単体金属または合金の地金を、直接、混合溶媒に混入し、溶解させることをいう。乾燥は、還元雰囲気下で行われることが望ましい。乾燥温度は、例えば５０〜３００℃である。熱処理は、酸化防止のために水素雰囲気や窒素雰囲気などの還元雰囲気下で行われることが望ましい。熱処理温度は、例えば４００〜６００℃である。 Here, after the solution for forming the light absorption layer 4 is applied to the surface of the lower electrode layer 3 and a film is formed by drying, the film is heat-treated to form the light absorption layer 4. . The solution for forming the light absorption layer 4 is prepared by directly dissolving the group IB metal and the group III-B metal in a solvent containing a chalcogen element-containing compound and a basic organic solvent. The total concentration of the group B metal and the group III-B metal is 10% by mass or more. Various methods such as spin coater, screen printing, dipping, spraying, and die coater can be applied to the solution. The chalcogen element-containing organic compound is an organic compound containing a chalcogen element. As a chalcogen element, S, Se, and Te among VI-B group elements are said. Examples of the chalcogen element-containing organic compound include thiol, sulfide, selenol, tellurol and the like. To directly dissolve a metal in a mixed solvent means to dissolve a single metal or alloy ingot directly into the mixed solvent and dissolve it. Drying is desirably performed in a reducing atmosphere. The drying temperature is, for example, 50 to 300 ° C. The heat treatment is desirably performed in a reducing atmosphere such as a hydrogen atmosphere or a nitrogen atmosphere in order to prevent oxidation. The heat treatment temperature is, for example, 400 to 600 ° C.
光吸収層４が形成された後、半導体層５はＣＢＤ法（ケミカルバス成膜法）によって形成される（図４を参照）。 After the light absorption layer 4 is formed, the semiconductor layer 5 is formed by a CBD method (chemical bath film formation method) (see FIG. 4).
ここで本実施形態の製造方法は、下部電極層上に、Ｉ−Ｂ族元素、III−Ｂ族元素およびVI−Ｂ族元素を含む光吸収層を形成する第１工程と、光吸収層上に、III−Ｂ族元素およびVI−Ｂ族元素を含む第１半導体層をＣＢＤ法で形成するとともに、ＣＢＤ法における成膜用溶液のＩｎの原子％ＣＩｎと硫黄の原子％ＣＳとが、ＣＩｎ：ＣＳ＝１：１〜９（好ましくは２）となるように制御する第２工程とを有することが好ましい。Here, the manufacturing method of the present embodiment includes a first step of forming a light absorption layer containing a group IB element, a group III-B element, and a group VI-B element on the lower electrode layer, In addition, the first semiconductor layer containing the III-B group element and the VI-B group element is formed by the CBD method, and the atomic% C In and sulfur atomic% C S of the film-forming solution in the CBD method are , C In : C S = 1: 1 to 9 (preferably 2).
そしてこの第２工程では、半導体層５のエピタキシャル成長中に、成膜用溶液の循環流量と、そのバブリング用窒素の流量とを制御し、成膜用溶液中の凝集物の平均粒径を３００ｎｍ以上５００ｎｍ未満、成膜用溶液の成膜温度を６５℃以上７０℃未満、ｐＨ２．４以上ｐＨ２．６未満の範囲となるように管理する。 In this second step, during the epitaxial growth of the semiconductor layer 5, the circulation flow rate of the film-forming solution and the flow rate of the bubbling nitrogen are controlled so that the average particle size of the aggregates in the film-forming solution is 300 nm or more. The film forming temperature is controlled to be less than 500 nm, the film forming temperature of the film forming solution is in the range of 65 ° C. or higher and lower than 70 ° C., pH 2.4 or higher and lower than pH 2.6.
そして、成膜用溶液中の凝集物の平均粒径を３μｍ以上、成膜用溶液をｐＨ２．６以上２．８未満に切り替えることによって、エピタキシャル成長後に針状結晶を個別に成長させつつ、その成長過程で針状結晶を面内方向に成長させて融合させ、上部電極層７側に多数の空孔５ｂを有する多孔質層領域５ａを成長させる（図５を参照）。 Then, by changing the average particle size of the aggregates in the film-forming solution to 3 μm or more and the film-forming solution to pH 2.6 or more and less than 2.8, the needle-like crystals are grown individually after the epitaxial growth, and the growth is performed. In the process, acicular crystals are grown and fused in the in-plane direction to grow a porous layer region 5a having a large number of holes 5b on the upper electrode layer 7 side (see FIG. 5).
これにより、周囲が第１半導体層５のみで囲まれた空孔５ｂを得ることができる。 As a result, it is possible to obtain a hole 5 b that is surrounded by only the first semiconductor layer 5.
ここで、ｐｈは塩酸、酢酸、硝酸の少なくともいずれかの酸もしくはアンモニア水を添加することによって制御することができる。 Here, ph can be controlled by adding at least one of hydrochloric acid, acetic acid and nitric acid, or aqueous ammonia.
また、平均粒度は、成膜用溶液を遠心分離法で分粒することによって、粒度分布を管理することができる。 The average particle size can be controlled by dividing the film-forming solution by centrifugal separation.
そして、上部電極層７をスパッタリング法で形成する際に、多孔質層領域５ａによってスパッタリング粒子のピンニングを捕捉することができる（図６を参照）。 Then, when the upper electrode layer 7 is formed by the sputtering method, pinning of the sputtered particles can be captured by the porous layer region 5a (see FIG. 6).
そして、上部電極層７として錫を含んだ酸化イジウム（ＩＴＯ）などが、スパッタリング法、蒸着法で形成される（図７、図８および図９を参照）。 Then, iridium oxide (ITO) containing tin or the like is formed as the upper electrode layer 7 by a sputtering method or a vapor deposition method (see FIGS. 7, 8, and 9).
（第２実施形態の光電変換素子の製造方法）
ここでは光吸収層１４までの形成は、上記第１実施形態と同様である。(Method for Manufacturing Photoelectric Conversion Element of Second Embodiment)
Here, the formation up to the light absorption layer 14 is the same as in the first embodiment.
光吸収層１４が形成された後、第１半導体層１５はＣＢＤ法（ケミカルバス成膜法）によって形成されるが、後工程で第２半導体層１６をスパッタリング法で形成する場合には、光吸収層１４をダメージから保護できる厚みであることが好ましい（図１２を参照）。 After the light absorption layer 14 is formed, the first semiconductor layer 15 is formed by a CBD method (chemical bath film formation method). However, when the second semiconductor layer 16 is formed by a sputtering method in a later process, The thickness is preferably such that the absorption layer 14 can be protected from damage (see FIG. 12).
ここで、本実施形態の製造方法は、下部電極層１３上に、Ｉ−Ｂ族元素、III−Ｂ族元素およびVI−Ｂ族元素を含む光吸収層１４を形成する第１工程と、光吸収層１４上に、III−Ｂ族元素およびVI−Ｂ族元素を含む第１半導体層１５をＣＢＤ法で形成するとともに、ＣＢＤ法における成膜用溶液のＩｎの原子％ＣＩｎと硫黄の原子％ＣＳとが、ＣＩｎ：ＣＳ＝１：１〜９（好ましくは２）となるように制御する第２工程とを有することが好ましい。Here, the manufacturing method of the present embodiment includes a first step of forming a light absorption layer 14 containing a group IB element, a group III-B element, and a group VI-B element on the lower electrode layer 13, a light A first semiconductor layer 15 containing a group III-B element and a group VI-B element is formed on the absorption layer 14 by the CBD method, and the atomic% C In and sulfur atoms of the film-forming solution in the CBD method It is preferable to have a second step of controlling% C S so that C In : C S = 1: 1 to 9 (preferably 2).
そしてこの第２工程では、第１半導体層１５のエピタキシャル成長中に、成膜用溶液の循環流量と、そのバブリング用窒素の流量とを制御し、成膜用溶液中の凝集物の平均粒径を３００ｎｍ以上５００ｎｍ未満、成膜用溶液の成膜温度を６５℃以上７０℃未満、ｐＨ２．４以上ｐＨ２．６未満の範囲となるように管理する。 In this second step, during the epitaxial growth of the first semiconductor layer 15, the circulation flow rate of the film forming solution and the flow rate of the bubbling nitrogen are controlled, and the average particle size of the aggregates in the film forming solution is determined. The film-forming temperature of the film-forming solution is controlled to be in the range of from 65 to 70 ° C. and from pH 2.4 to less than 2.6.
そして、成膜用溶液中の凝集物の平均粒径を３μｍ以上、成膜用溶液をｐＨ２．６以上２．８未満に切り替えることによって、エピタキシャル成長後に針状結晶を個別に成長させつつ、その成長過程で針状結晶を面内方向に成長させて融合させ、上部電極層１７側に多数の空孔５ｂを有する第１多孔質層領域１５ａを成長させる（図１３を参照）。 Then, by changing the average particle size of the aggregates in the film-forming solution to 3 μm or more and the film-forming solution to pH 2.6 or more and less than 2.8, the needle-like crystals are grown individually after the epitaxial growth, and the growth is performed. In the process, acicular crystals are grown in the in-plane direction and fused to grow a first porous layer region 15a having a large number of holes 5b on the upper electrode layer 17 side (see FIG. 13).
これにより、周囲が第１半導体層１５のみで囲まれた空孔１５ｂを得ることができる。 As a result, it is possible to obtain a hole 15 b whose periphery is surrounded only by the first semiconductor layer 15.
ここで、ｐｈは塩酸、酢酸、硝酸の少なくともいずれかの酸もしくはアンモニア水を添加することによって制御することができる。 Here, ph can be controlled by adding at least one of hydrochloric acid, acetic acid and nitric acid, or aqueous ammonia.
また、平均粒度は成、膜用溶液を遠心分離法で分粒することによって、粒度分布を管理することができる。 Further, the average particle size can be controlled, and the particle size distribution can be managed by sizing the membrane solution by centrifugal separation.
そして、第２半導体層１６をスパッタリング法で形成する際に、第１多孔質層領域１５ａにおいてピンニングされたスパッタリング粒子を捕捉することができる（図１４および図１５を参照）。 And when forming the 2nd semiconductor layer 16 by sputtering method, the sputtering particle pinned in the 1st porous layer area | region 15a can be capture | acquired (refer FIG. 14 and FIG. 15).
そして、上部電極層１７として錫を含んだ酸化インジウム（ＩＴＯ）などが、スパッタリング法、蒸着法で形成される（図１６、図１７および図１８を参照）。 Then, indium oxide (ITO) containing tin or the like is formed as the upper electrode layer 17 by a sputtering method or a vapor deposition method (see FIGS. 16, 17, and 18).
（実施例１）第１実施形態の光電変換素子
（試料作製）
本実施例１は、半導体層が単層構造である場合に関するものである。Example 1 Photoelectric Conversion Element of First Embodiment (Sample Preparation)
Example 1 relates to the case where the semiconductor layer has a single layer structure.
洗浄されたガラス基板２の略全面に、Ｍｏからなる下部電極層３をスパッタリング法で形成し、下部電極層３上に光吸収層４（Ｃｕ、Ｉｎ、ＧａおよびＳｅを含むＣＩＧＳ）を塗布法を用いて形成した。 A lower electrode layer 3 made of Mo is formed on substantially the entire surface of the cleaned glass substrate 2 by a sputtering method, and a light absorption layer 4 (CIGS containing Cu, In, Ga and Se) is applied on the lower electrode layer 3 Formed using.
光吸収層４を形成するための溶液の濃度は１０質量％とし、スピンコーターで塗布して、乾燥温度は５０℃で１時間、熱処理は窒素雰囲気下で４００℃で１時間とした。 The concentration of the solution for forming the light absorption layer 4 was 10% by mass, applied with a spin coater, the drying temperature was 50 ° C. for 1 hour, and the heat treatment was performed in a nitrogen atmosphere at 400 ° C. for 1 hour.
光吸収層４が形成された後、半導体層５はＣＢＤ法（ケミカルバス成膜法）によって形成し、後工程で上部電極層７をスパッタリング法で形成した。 After the light absorption layer 4 was formed, the semiconductor layer 5 was formed by a CBD method (chemical bath film formation method), and the upper electrode layer 7 was formed by a sputtering method in a later step.
そして、半導体層５のエピタキシャル成長中に、成膜用溶液の循環流量と、そのバブリング用窒素の流量を制御し、成膜用溶液中の凝集物の平均粒径を３００ｎｍ、成膜用溶液の成膜温度を６５℃、ｐＨ２．４となるように管理した。そして、成膜用溶液中の凝集物の平均粒径を３μｍ、成膜用溶液をｐＨ２．６に切り替えることによって、エピタキシャル成長後に針状結晶を個別に成長させつつ、その成長過程で針状結晶を面内方向に成長させて融合させ、半導体層５全体としては１００ｎｍ厚とした。そして、上部電極層７側に多数の空孔５ｂを有する多孔質層領域５ａを成長させ、上部電極層７として酸化インジウム（ＩＴＯ）をスパッタリング法で形成した。 Then, during the epitaxial growth of the semiconductor layer 5, the circulation flow rate of the film-forming solution and the flow rate of the bubbling nitrogen are controlled so that the average particle size of the aggregates in the film-forming solution is 300 nm, and the film-forming solution is formed. The membrane temperature was controlled to 65 ° C. and pH 2.4. Then, by switching the average particle size of the aggregate in the film-forming solution to 3 μm and the film-forming solution to pH 2.6, the needle-like crystals are grown in the growth process while growing the needle-like crystals individually after the epitaxial growth. The semiconductor layer 5 as a whole was grown to a thickness of 100 nm by growing in the in-plane direction and fusing. And the porous layer area | region 5a which has many holes 5b on the upper electrode layer 7 side was grown, and indium oxide (ITO) was formed as the upper electrode layer 7 by sputtering method.
比較例１として、半導体層５のエピタキシャル成長中に、成膜用溶液の循環流量と、そのバブリング用窒素の流量とを制御し、成膜用溶液中の凝集物の平均粒径を３００ｎｍ、成膜用溶液の成膜温度を６５℃、ｐＨ２．４となるように管理した後に、針状結晶が発生する前に成膜を止めて、上部電極層７として酸化インジウム（ＩＴＯ）をスパッタリング法で形成したことで、多孔質層領域５ａを有さない試料１とした。 As Comparative Example 1, during the epitaxial growth of the semiconductor layer 5, the circulation flow rate of the film forming solution and the flow rate of the bubbling nitrogen are controlled, and the average particle size of the aggregates in the film forming solution is 300 nm. After controlling the film forming temperature of the solution to 65 ° C. and pH 2.4, the film forming is stopped before the needle-like crystals are generated, and indium oxide (ITO) is formed as the upper electrode layer 7 by the sputtering method. Thus, Sample 1 without the porous layer region 5a was obtained.
以下、結果を表１に示す。なお多孔質層領域５ａの空孔率は、多孔質層領域５ａの成膜速度で、多孔質層領域５ａの厚さは、多孔質層領域５ａの成膜時間でそれぞれ制御した。 The results are shown in Table 1. The porosity of the porous layer region 5a was controlled by the deposition rate of the porous layer region 5a, and the thickness of the porous layer region 5a was controlled by the deposition time of the porous layer region 5a.
比較例である試料１では、上部電極層７をスパッタリング法で形成したとき、スパッタリング粒子のピンニング（打ち込み）によるダメージによって、半導体層５が壊れて光吸収層４とのｐｎ接合界面に欠陥が生じていたため、光電変換効率が低かった。 In the sample 1 as a comparative example, when the upper electrode layer 7 is formed by the sputtering method, the semiconductor layer 5 is broken due to damage caused by pinning (striking) of the sputtered particles, and a defect is generated at the pn junction interface with the light absorption layer 4. Therefore, the photoelectric conversion efficiency was low.
試料２〜６において、特に試料３〜５では良好な光電変換効率を示した。 In Samples 2-6, Samples 3-5 showed good photoelectric conversion efficiency.
また試料７〜１１において、特に試料８〜１０では良好な光電変換効率を示し、多孔質層領域５ａの厚さは５〜７０ｎｍである場合に、好適範囲を示すことがわかった。 Moreover, in the samples 7-11, especially the samples 8-10 showed favorable photoelectric conversion efficiency, and when the thickness of the porous layer area | region 5a was 5-70 nm, it turned out that a suitable range is shown.
なお、本実施例である試料２〜１１の断面をＴＥＭで観察すれば、半導体層５の上部電極層７側に空孔５ｂが多く分布していた。 In addition, if the cross section of the samples 2-11 which are a present Example is observed by TEM, many holes 5b were distributed in the upper electrode layer 7 side of the semiconductor layer 5. FIG.
（実施例２）第２実施形態の光電変換素子
（試料作製）
本実施例２は、半導体層が２層構造である場合に関するものである。Example 2 Photoelectric Conversion Element of Second Embodiment (Sample Preparation)
Example 2 relates to a case where the semiconductor layer has a two-layer structure.
光吸収層１４を形成するまでは実施例１と同様である。 The process is the same as in Example 1 until the light absorption layer 14 is formed.
そして、第１半導体層１５のエピタキシャル成長中に、成膜用溶液の循環流量と、そのバブリング用窒素の流量とを制御し、成膜用溶液中の凝集物の平均粒径を３００ｎｍ、成膜用溶液の成膜温度を６５℃、ｐＨ２．４となるように管理した。 During the epitaxial growth of the first semiconductor layer 15, the circulation flow rate of the film formation solution and the flow rate of the bubbling nitrogen are controlled so that the average particle size of the aggregates in the film formation solution is 300 nm. The film formation temperature of the solution was controlled to 65 ° C. and pH 2.4.
そして、成膜用溶液中の凝集物の平均粒径を３μｍ、成膜用溶液をｐＨ２．６に切り替えることによって、エピタキシャル成長後に針状結晶を個別に成長させつつ、その成長過程で針状結晶を面内方向に成長させて融合させ、第２半導体層１６側に多数の空孔１５ｂを有する多孔質層領域１５ａを成長させ、半導体層５全体としては１００ｎｍ厚とした。 Then, by switching the average particle size of the aggregate in the film-forming solution to 3 μm and the film-forming solution to pH 2.6, the needle-like crystals are grown in the growth process while growing the needle-like crystals individually after the epitaxial growth. The porous layer region 15a having a large number of pores 15b on the second semiconductor layer 16 side is grown in the in-plane direction and fused, and the semiconductor layer 5 as a whole has a thickness of 100 nm.
そして、第２半導体層１６として高抵抗な酸化亜鉛（ｉ−ＺｎＯ）を、上部電極層１７として酸化インジウム（ＩＴＯ）をスパッタリング法で形成した。 Then, high resistance zinc oxide (i-ZnO) was formed as the second semiconductor layer 16 and indium oxide (ITO) was formed as the upper electrode layer 17 by sputtering.
比較例１として、第１半導体層１５のエピタキシャル成長中に、成膜用溶液の循環流量と、そのバブリング用窒素の流量とを制御し、成膜用溶液中の凝集物の平均粒径を３００ｎｍ、成膜用溶液の成膜温度を６５℃、ｐＨ２．４となるように管理した後に、針状結晶が発生する前に成膜を止めて、第２半導体層１６として高抵抗な酸化亜鉛（ｉ−ＺｎＯ）を、上部電極層７として酸化インジウム（ＩＴＯ）をスパッタリング法で形成したことで、多孔質層領域１５ａを有さない試料１２とした。 As Comparative Example 1, during the epitaxial growth of the first semiconductor layer 15, the circulation flow rate of the film formation solution and the flow rate of the bubbling nitrogen are controlled, and the average particle size of the aggregates in the film formation solution is 300 nm. After the film-forming temperature of the film-forming solution is controlled to be 65 ° C. and pH 2.4, the film formation is stopped before the acicular crystals are generated, and high resistance zinc oxide (i -ZnO) was formed as a sample 12 having no porous layer region 15a by forming indium oxide (ITO) as the upper electrode layer 7 by a sputtering method.
以下、結果を表２に示す。なお第１多孔質層領域１５ａの空孔率は、第１多孔質層領域１５ａの成膜速度で、第１多孔質層領域１５ａの厚さは、第１多孔質層領域１５ａの成膜時間でそれぞれ制御した。 The results are shown in Table 2 below. The porosity of the first porous layer region 15a is the film formation speed of the first porous layer region 15a, and the thickness of the first porous layer region 15a is the film formation time of the first porous layer region 15a. Respectively.
比較例である試料１２では、第２半導体層１６をスパッタリング法で形成したとき、スパッタリング粒子のピンニング（打ち込み）によるダメージによって、第１半導体層１５が壊れて光吸収層１４とのｐｎ接合界面に欠陥が生じていたため、光電変換効率が低かった。 In the sample 12 as a comparative example, when the second semiconductor layer 16 is formed by the sputtering method, the first semiconductor layer 15 is broken due to damage caused by pinning (implantation) of the sputtered particles, and the pn junction interface with the light absorption layer 14 is formed. Since a defect occurred, the photoelectric conversion efficiency was low.
試料１３〜１７において、特に試料１４〜１６では良好な光電変換効率を示した。 In Samples 13-17, Samples 14-16 showed good photoelectric conversion efficiency.
また試料１８〜２２において、特に試料１９〜２１では良好な光電変換効率を示し、多孔質層領域５ａの厚さは、５〜７０ｎｍである場合に、好適範囲であることがわかった。 Moreover, in the samples 18-22, especially the samples 19-21 showed favorable photoelectric conversion efficiency, and when the thickness of the porous layer area | region 5a was 5-70 nm, it turned out that it is a suitable range.
なお、本実施例である試料１３〜２２の断面をＴＥＭで観察したところ、第１半導体層５の第２半導体層６側に空孔５ｂが多く分布していた。 In addition, when the cross section of the samples 13-22 which are a present Example was observed by TEM, many holes 5b were distributed by the 2nd semiconductor layer 6 side of the 1st semiconductor layer 5. FIG.
１、１１：光電変換素子
２、１２：基板
３、１３：下部電極層
４、１４：光吸収層
５：半導体層
５ａ：多孔質層領域
５ｂ：空孔
１５：第１半導体層
１５ａ：第１多孔質層領域
１５ｂ：空孔
１６：第２半導体層
７、１７：上部電極層
８：グリッド電極DESCRIPTION OF SYMBOLS 1, 11: Photoelectric conversion element 2, 12: Board | substrate 3, 13: Lower electrode layer 4, 14: Light absorption layer 5: Semiconductor layer 5a: Porous layer area | region 5b: Hole 15: 1st semiconductor layer 15a: 1st Porous layer region 15b: Hole 16: Second semiconductor layer 7, 17: Upper electrode layer 8: Grid electrode
Claims (11)
前記半導体層は、前記上部電極層側に、多数の空孔を有する多孔質層領域を有する光電変換素子。A lower electrode layer, a light absorption layer including a compound semiconductor capable of photoelectric conversion provided on the lower electrode layer, a semiconductor layer provided on the light absorption layer, and provided on the semiconductor layer; A photoelectric conversion element having an upper electrode layer having a lower electrical resistivity than the semiconductor layer,
The said semiconductor layer is a photoelectric conversion element which has a porous layer area | region which has many void | holes in the said upper electrode layer side.
前記第１半導体層は、前記第２半導体層側に、多数の空孔を有する第１多孔質層領域を有する、光電変換素子。A lower electrode layer, a light absorption layer including a compound semiconductor capable of photoelectric conversion provided on the lower electrode layer, a first semiconductor layer provided on the light absorption layer, and the first semiconductor layer; A photoelectric conversion element comprising: a second semiconductor layer provided; and an upper electrode layer provided on the second semiconductor layer and having a lower resistivity than the second semiconductor layer,
The first semiconductor layer has a first porous layer region having a large number of pores on the second semiconductor layer side.
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