JPWO2008093626A1 - チップ素子およびその製造方法 - Google Patents
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Abstract
Description
10,60,80…誘電体基板
11,61…スルーホール
12,62,82…主面電極
13,63,83…接地電極
20,70,90,95…ガラス層
21,71,96…ボンディング用電極
50…金ワイヤ
22,72,97…開口
73…下地電極
92…銀電極
(S1)まず、いずれの面にも電極を形成していない誘電体親基板を用意する。
(S2)次に、上記親基板に対して、裏主面側に導電体ペーストをスクリーン印刷し、焼成を経て接地電極および端子電極を形成する。
(S3)次に、親基板に対して、表主面側に感光性銀電極ペーストを印刷し、露光、現像するフォトリソグラフィプロセスによりパターンを形成し、その後、焼成して各主面電極を形成する。
(S4)次に、親基板の表主面側に絶縁性材を主成分とし感光性材を添加した感光性ガラスペーストを印刷し、フォトマスクを用いて前記ペーストを露光し、固化していない前記ペーストを除去して開口を設ける現像を行うフォトリソグラフィプロセスによりパターンを形成し、その後、焼成を経てガラス層を形成する。なお、この工程に用いる露光装置などは、上記主面電極の形成工程で用いたものとする。これにより、露光装置などを複数用意する必要が無くなり製造コストの削減が可能になる。
(S5)次に、親基板の表主面側全体を複数回、メッキ液を異ならせながらメッキ浴する。最初にメッキ浴に用いるメッキ液は、銀電極に対してメッキ性があり、ガラス層に対してメッキ性のないニッケルを主成分とするものとする。また、最後にメッキ浴に用いるメッキ液は、金ワイヤとのボンディング性に優れ、ガラス層に対してメッキ性のない金を主成分とするものとする。
Claims (10)
- 表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子において、
前記電極パターン上に開口を形成して前記基体の表主面に形成した、前記複数のメッキ層に対して非メッキ性を有する絶縁膜を備え、
前記絶縁膜に設けた開口内に露出する前記電極パターンを下地電極として、前記下地電極上に前記複数のメッキ層をメッキして、前記ボンディング用電極を形成したことを特徴とするチップ素子。 - 表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子において、
前記電極パターン上に開口を形成して前記基体の表主面に積層した、前記複数のメッキ層に対して非メッキ性を有する絶縁膜と、
前記絶縁膜の開口に設けた導体を介して前記電極パターンに導通する、前記絶縁膜の表主面に配した下地電極と、
を備え
前記下地電極上に、前記複数のメッキ層をメッキして、前記ボンディング用電極を形成したことを特徴とするチップ素子。 - 前記基体は、複数の絶縁層を積層して、前記絶縁層間にも電極パターンを設けた構成である請求項1又は2に記載のチップ素子。
- 表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子において、
前記電極パターン上に開口を形成して前記基体の表主面に積層した第1の絶縁膜と、
前記第1の絶縁膜の開口に設けた導体を介して前記電極パターンに導通する、前記第1の絶縁膜の表主面に配した絶縁膜上電極パターンと、
前記絶縁膜上電極パターン上に開口を形成して前記第1の絶縁膜の表主面に積層した第2の絶縁膜と、
前記第2の絶縁膜の開口に設けた導体を介して前記絶縁膜上電極パターンに導通する、前記第2の絶縁膜の表主面に配した下地電極と、
を備え、
前記第2の絶縁膜は、前記複数のメッキ層に対して非メッキ性を有し、
前記下地電極上に、前記複数のメッキ層をメッキして、前記ボンディング用電極を形成したことを特徴とするチップ素子。 - 前記ボンディング用電極は、前記金メッキ層下に、前記金メッキ層よりも前記下地電極に対しての接着性が高い下地メッキ層を備える請求項1〜4のいずれかに記載のチップ素子。
- 前記下地電極は銀を主成分とし、前記絶縁膜はケイ酸系ガラスを主成分とし、前記下地メッキ層はニッケルを主成分とする請求項5に記載のチップ素子。
- 前記絶縁膜はフォトリソグラフィプロセスにより前記開口を形成したものである請求項1〜6のいずれかに記載のチップ素子。
- 前記電極パターンを伝送線路としてマイクロストリップ線路フィルタを構成した請求項1〜7のいずれかに記載のチップ素子。
- 表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子の製造方法であって、
感光性材を分散させた絶縁性ペーストを前記基体に塗布し、フォトマスクを用いて前記絶縁性ペーストを感光させて固化し、固化していない前記絶縁性ペーストを除去して開口を設けて、前記複数のメッキ層に対して非メッキ性を有する絶縁膜を形成する絶縁膜形成工程と、
前記絶縁膜形成工程の後、前記開口の底面に複数回のメッキを施して前記複数のメッキ層を形成して前記ボンディング用電極を形成するボンディング用電極形成工程と、
を含むチップ素子の製造方法。 - 表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子の製造方法であって、
感光性材を分散させた絶縁性ペーストを前記基体に塗布し、フォトマスクを用いて前記絶縁性ペーストを感光させて固化し、固化していない前記絶縁性ペーストを除去して開口を設けて、前記複数のメッキ層に対して非メッキ性を有する絶縁膜を形成する絶縁膜形成工程と、
前記絶縁膜形成工程の後、感光性材を分散させた導電性ペーストを前記絶縁膜の表主面に塗布し、フォトマスクを用いて前記導電性ペーストを感光させて固化し、固化していない前記導電性ペーストを除去して、前記基体に設けた電極パターンに導通する下地電極を形成する下地電極形成工程と、
前記下地電極形成工程の後、前記下地電極上に、複数回のメッキを施して前記複数のメッキ層を形成して前記ボンディング用電極を形成するボンディング用電極形成工程と、
を含むチップ素子の製造方法。
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US8889995B2 (en) | 2011-03-03 | 2014-11-18 | Skyworks Solutions, Inc. | Wire bond pad system and method |
US9679869B2 (en) | 2011-09-02 | 2017-06-13 | Skyworks Solutions, Inc. | Transmission line for high performance radio frequency applications |
KR20190058711A (ko) | 2012-06-14 | 2019-05-29 | 스카이워크스 솔루션즈, 인코포레이티드 | 고조파 종단 회로를 포함하는 전력 증폭기 모듈 및 관련된 시스템, 장치, 및 방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60195961A (ja) * | 1984-03-19 | 1985-10-04 | Hitachi Ltd | 半導体装置 |
JPH06283566A (ja) * | 1993-03-25 | 1994-10-07 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2002016176A (ja) * | 2000-06-29 | 2002-01-18 | Kyocera Corp | 配線基板およびその接続構造 |
JP2002151908A (ja) * | 2000-11-14 | 2002-05-24 | Murata Mfg Co Ltd | 高周波フィルタおよびそれを用いたフィルタ装置およびそれらを用いた電子装置 |
JP2005322868A (ja) * | 2004-05-03 | 2005-11-17 | Samsung Electro Mech Co Ltd | プリント回路基板の電解金メッキ方法 |
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GB0108655D0 (en) * | 2001-04-06 | 2001-05-30 | Koninkl Philips Electronics Nv | Microwave circuit |
JP2003060428A (ja) * | 2001-08-21 | 2003-02-28 | Hitachi Ltd | 高周波回路装置及びその製造方法 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60195961A (ja) * | 1984-03-19 | 1985-10-04 | Hitachi Ltd | 半導体装置 |
JPH06283566A (ja) * | 1993-03-25 | 1994-10-07 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2002016176A (ja) * | 2000-06-29 | 2002-01-18 | Kyocera Corp | 配線基板およびその接続構造 |
JP2002151908A (ja) * | 2000-11-14 | 2002-05-24 | Murata Mfg Co Ltd | 高周波フィルタおよびそれを用いたフィルタ装置およびそれらを用いた電子装置 |
JP2005322868A (ja) * | 2004-05-03 | 2005-11-17 | Samsung Electro Mech Co Ltd | プリント回路基板の電解金メッキ方法 |
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