JPS6482548A - Formation of interconnection pattern - Google Patents

Formation of interconnection pattern

Info

Publication number
JPS6482548A
JPS6482548A JP23869387A JP23869387A JPS6482548A JP S6482548 A JPS6482548 A JP S6482548A JP 23869387 A JP23869387 A JP 23869387A JP 23869387 A JP23869387 A JP 23869387A JP S6482548 A JPS6482548 A JP S6482548A
Authority
JP
Japan
Prior art keywords
contact holes
layer
interconnection layer
sections
dummy contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23869387A
Other languages
Japanese (ja)
Inventor
Keisuke Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP23869387A priority Critical patent/JPS6482548A/en
Publication of JPS6482548A publication Critical patent/JPS6482548A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve adhesion properties between an interconnection layer and a resist layer formed thereon for improving yield of products, by forming dummy contact holes in an insulating layer in addition to proper contact holes, the dummy contact holes having no relation with electrical connections. CONSTITUTION:An element forming region 2 and an element isolating region 3 are formed on a semiconductor substrate 1. Polycrystalline silicon is deposited on the whole surface thereof and then it is patterned to form lower electrode layers 4a, 4b providing sections to be connected. An interlayer insulating film 5 is then formed all over the structure. The insulating layer 5 is provided with contact holes 6a, 6b opened directly over the sections to be connected and also with dummy contact holes 7 opened at any part other than the sections to be connected. An interconnection layer 8 is formed over there. A resist layer 10 is formed so as to cover recesses 9 produced on the surface of the interconnection layer 8 corresponding to said contact holes and dummy contact holes. Accordingly, the surface area of the interconnection layer is increased while mating effect can be obtained between the recesses and projections. In this manner, adhesion properties between the interconnection layer and the resist layer can be improved.
JP23869387A 1987-09-25 1987-09-25 Formation of interconnection pattern Pending JPS6482548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23869387A JPS6482548A (en) 1987-09-25 1987-09-25 Formation of interconnection pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23869387A JPS6482548A (en) 1987-09-25 1987-09-25 Formation of interconnection pattern

Publications (1)

Publication Number Publication Date
JPS6482548A true JPS6482548A (en) 1989-03-28

Family

ID=17033893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23869387A Pending JPS6482548A (en) 1987-09-25 1987-09-25 Formation of interconnection pattern

Country Status (1)

Country Link
JP (1) JPS6482548A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01152644A (en) * 1987-12-09 1989-06-15 Sharp Corp Semiconductor device
US5208214A (en) * 1988-12-29 1993-05-04 Hoechst Aktiengesellschaft Multiphase superconductor and process for its production
DE19527368C2 (en) * 1994-07-26 2001-09-13 Toshiba Kawasaki Kk Manufacturing method of a semiconductor device with single crystal wiring layers

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01152644A (en) * 1987-12-09 1989-06-15 Sharp Corp Semiconductor device
US5208214A (en) * 1988-12-29 1993-05-04 Hoechst Aktiengesellschaft Multiphase superconductor and process for its production
DE19527368C2 (en) * 1994-07-26 2001-09-13 Toshiba Kawasaki Kk Manufacturing method of a semiconductor device with single crystal wiring layers

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