JPS6480885A - Lsi testing circuit - Google Patents

Lsi testing circuit

Info

Publication number
JPS6480885A
JPS6480885A JP62240036A JP24003687A JPS6480885A JP S6480885 A JPS6480885 A JP S6480885A JP 62240036 A JP62240036 A JP 62240036A JP 24003687 A JP24003687 A JP 24003687A JP S6480885 A JPS6480885 A JP S6480885A
Authority
JP
Japan
Prior art keywords
test
basic clock
combination circuit
operates
testing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62240036A
Other languages
Japanese (ja)
Inventor
Shiro Yoshimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62240036A priority Critical patent/JPS6480885A/en
Publication of JPS6480885A publication Critical patent/JPS6480885A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To compose a shift register of all FFs at the time of a test and to conduct the test by providing an FF for observation in front of an FF which operates asynchronously with basic clock pulses. CONSTITUTION:The output of the combination circuit 107 of the LSI consisting of the combination circuit 100, the FF 106 which operates in synchronism with the basic clock, the combination circuit 107 which generates a clock asynchronous with the basic clock, and an FF 108 which operates according to it is connected to the FF 109 for observation. The when the test is conducted, the output terminal of the precedent FF 106 is connected to this FF 109, whose output is connected to the FF 108. Consequently, the scan path incorporation circuit wherein the FFs 106, 109, and 108 form one shift register is constituted at the time of the test and all circuits are tested simultaneously.
JP62240036A 1987-09-24 1987-09-24 Lsi testing circuit Pending JPS6480885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62240036A JPS6480885A (en) 1987-09-24 1987-09-24 Lsi testing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62240036A JPS6480885A (en) 1987-09-24 1987-09-24 Lsi testing circuit

Publications (1)

Publication Number Publication Date
JPS6480885A true JPS6480885A (en) 1989-03-27

Family

ID=17053514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62240036A Pending JPS6480885A (en) 1987-09-24 1987-09-24 Lsi testing circuit

Country Status (1)

Country Link
JP (1) JPS6480885A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7082559B2 (en) 2001-03-07 2006-07-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device and test method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7082559B2 (en) 2001-03-07 2006-07-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device and test method thereof
US7139956B2 (en) 2001-03-07 2006-11-21 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device and test method thereof

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