JPS6480128A - Programmable logic device - Google Patents

Programmable logic device

Info

Publication number
JPS6480128A
JPS6480128A JP62238160A JP23816087A JPS6480128A JP S6480128 A JPS6480128 A JP S6480128A JP 62238160 A JP62238160 A JP 62238160A JP 23816087 A JP23816087 A JP 23816087A JP S6480128 A JPS6480128 A JP S6480128A
Authority
JP
Japan
Prior art keywords
bus
bus line
address
line
programmable circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62238160A
Other languages
Japanese (ja)
Other versions
JPH0517572B2 (en
Inventor
Keiichi Kawana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP62238160A priority Critical patent/JPS6480128A/en
Publication of JPS6480128A publication Critical patent/JPS6480128A/en
Publication of JPH0517572B2 publication Critical patent/JPH0517572B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)

Abstract

PURPOSE:To use a signal line effectively and to decrease the number of signal lines forming the bus line by providing the bus line where lots of kinds of signals coexist in time division through the detection of the address between at least two or over of programmable circuits. CONSTITUTION:An n-bit data bus 5, an m-bit control address bus 6 and a clock line 7 are arranged to a bus line region 4, and bus lines 5-7 are connected to all or a prescribed part of the programmable circuit 1. The programmable circuit 1 being a caller uses a proper means such as monitor of a specific bit to monitor an idle bus line and the address specific to the other programmable circuit 1 at the receiver side desiring to transmit/receive the data is sent to a control/address bus 6. When the transmission/reception of data is finished, floating state, for example, is attained to release the bus line thereby allowing other programmable circuit 1 to use the bus line.
JP62238160A 1987-09-22 1987-09-22 Programmable logic device Granted JPS6480128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62238160A JPS6480128A (en) 1987-09-22 1987-09-22 Programmable logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62238160A JPS6480128A (en) 1987-09-22 1987-09-22 Programmable logic device

Publications (2)

Publication Number Publication Date
JPS6480128A true JPS6480128A (en) 1989-03-27
JPH0517572B2 JPH0517572B2 (en) 1993-03-09

Family

ID=17026078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62238160A Granted JPS6480128A (en) 1987-09-22 1987-09-22 Programmable logic device

Country Status (1)

Country Link
JP (1) JPS6480128A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102841A (en) * 1991-10-07 1993-04-23 Nippon Telegr & Teleph Corp <Ntt> Digital processing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102841A (en) * 1991-10-07 1993-04-23 Nippon Telegr & Teleph Corp <Ntt> Digital processing circuit

Also Published As

Publication number Publication date
JPH0517572B2 (en) 1993-03-09

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