JPS6441970A - Vector arithmetic unit - Google Patents

Vector arithmetic unit

Info

Publication number
JPS6441970A
JPS6441970A JP19871087A JP19871087A JPS6441970A JP S6441970 A JPS6441970 A JP S6441970A JP 19871087 A JP19871087 A JP 19871087A JP 19871087 A JP19871087 A JP 19871087A JP S6441970 A JPS6441970 A JP S6441970A
Authority
JP
Japan
Prior art keywords
data
zero
input
memory
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19871087A
Other languages
Japanese (ja)
Inventor
Takashi Fujimori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19871087A priority Critical patent/JPS6441970A/en
Publication of JPS6441970A publication Critical patent/JPS6441970A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To speed up a processing by limiting the input of zero data to an arithmetic part and omitting a vector operation by the zero data when the zero data are detected by a zero detecting part. CONSTITUTION:When the zero data are detected by a zero detecting circuit 9, the appearing pattern of the zero data is transmitted to an arithmetic part control circuit 14 through an input part control circuit 10. By the zero pattern, the arithmetic part control circuit 14 knows, for example, at which point of time data to be set to a memory 7 for input data should be canceled, does not set the data of the memory 7 at the point of time and sets the data in, for example, a memory 6 for the input data to store next data. Thus, a wasteful operation for one cycle can be omitted and improve the efficiency of the processing.
JP19871087A 1987-08-08 1987-08-08 Vector arithmetic unit Pending JPS6441970A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19871087A JPS6441970A (en) 1987-08-08 1987-08-08 Vector arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19871087A JPS6441970A (en) 1987-08-08 1987-08-08 Vector arithmetic unit

Publications (1)

Publication Number Publication Date
JPS6441970A true JPS6441970A (en) 1989-02-14

Family

ID=16395724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19871087A Pending JPS6441970A (en) 1987-08-08 1987-08-08 Vector arithmetic unit

Country Status (1)

Country Link
JP (1) JPS6441970A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03166824A (en) * 1989-11-27 1991-07-18 Hitachi Ltd Decoding system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03166824A (en) * 1989-11-27 1991-07-18 Hitachi Ltd Decoding system

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