JPS6476770A - Insulated-gate bipolar transistor - Google Patents
Insulated-gate bipolar transistorInfo
- Publication number
- JPS6476770A JPS6476770A JP23342187A JP23342187A JPS6476770A JP S6476770 A JPS6476770 A JP S6476770A JP 23342187 A JP23342187 A JP 23342187A JP 23342187 A JP23342187 A JP 23342187A JP S6476770 A JPS6476770 A JP S6476770A
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- electrode
- contact
- forth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To adjust the trade-off relation between latching current and ON voltage, by making a first electrode come into contact with a first region, making a second electrode come into contact with both a third region and a forth region, and specifying the width and the dosage of the third region sandwiched between a second region and the forth region. CONSTITUTION:On an N<+> substrate 1 of a first region, is formed a low impurity concentration P<-> layer 2 as a second region, on the surface of which an N-layer 3 of a third region is selectively formed. On the surface of the N-layer, a P<+> layer 4 of a forth region is selectively formed. A surface region of the N-layer 3 sandwiched between the P<-> layer 2 and the P<+> layer 4 is made a channel region, and thereon a gate electrode 6 is formed, via a gate insulating film 5. A source electrode 7 is brought into contact with a deep N<+> layer 9 formed on the far side from the date electrode 6 of the N-layer 3 and the P<+> layer 4, in such a manner as to bridge them. A drain electrode 8 is brought into contact with the N<+> layer 1. The width (w) of the channel region 3 is 2-8mum, and the dosage of ion implantation to turn the channel region 3 into an N-pole is 1X10<13>-4X10<14>/cm<2>. The main carrier is electron, and the latching limit current is doubled or more as compared with prior ones.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23342187A JPS6476770A (en) | 1987-09-17 | 1987-09-17 | Insulated-gate bipolar transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23342187A JPS6476770A (en) | 1987-09-17 | 1987-09-17 | Insulated-gate bipolar transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6476770A true JPS6476770A (en) | 1989-03-22 |
Family
ID=16954793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23342187A Pending JPS6476770A (en) | 1987-09-17 | 1987-09-17 | Insulated-gate bipolar transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6476770A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5101241A (en) * | 1989-11-20 | 1992-03-31 | Kabushiki Kaisha Toshiba | Telescopic paper guide means movable to selected receiving trays |
-
1987
- 1987-09-17 JP JP23342187A patent/JPS6476770A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5101241A (en) * | 1989-11-20 | 1992-03-31 | Kabushiki Kaisha Toshiba | Telescopic paper guide means movable to selected receiving trays |
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