JPS6472394A - Synchronous type semiconductor storage device - Google Patents

Synchronous type semiconductor storage device

Info

Publication number
JPS6472394A
JPS6472394A JP62228732A JP22873287A JPS6472394A JP S6472394 A JPS6472394 A JP S6472394A JP 62228732 A JP62228732 A JP 62228732A JP 22873287 A JP22873287 A JP 22873287A JP S6472394 A JPS6472394 A JP S6472394A
Authority
JP
Japan
Prior art keywords
internal clock
clk2
latching circuit
memory part
transparent latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62228732A
Other languages
Japanese (ja)
Inventor
Atsushi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62228732A priority Critical patent/JPS6472394A/en
Publication of JPS6472394A publication Critical patent/JPS6472394A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To execute a high speed operation by controlling both a transparent latch of an address input side of a memory and a latching circuit of a data output side, by an internal clock pulse. CONSTITUTION:To an internal clock generating circuit 26, an external clock pulse is supplied, and from an input time point of one of its leading edge and trailing edge, internal clock pulses CLK1, CLK2 of prescribed width, which have been allowed to conform with an operation of a memory part 23 are generated, and by these internal clock pulses CLK1, CLK2, a transparent latch 24 and a latching circuit 25 are controlled, respectively. The transparent latch 24 is connected to an address input terminal of the memory part 23, and the latching circuit 25 is connected to a data output terminal of the memory part 23. Also, the latching circuit 25 executes a latching operation by the internal clock pulse CLK2. In such a way, a high speed operation can be executed.
JP62228732A 1987-09-11 1987-09-11 Synchronous type semiconductor storage device Pending JPS6472394A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62228732A JPS6472394A (en) 1987-09-11 1987-09-11 Synchronous type semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62228732A JPS6472394A (en) 1987-09-11 1987-09-11 Synchronous type semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6472394A true JPS6472394A (en) 1989-03-17

Family

ID=16880945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62228732A Pending JPS6472394A (en) 1987-09-11 1987-09-11 Synchronous type semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6472394A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287327A (en) * 1990-11-20 1994-02-15 Oki Electric Industry Co., Ltd. Synchronous dynamic random access memory
US5341341A (en) * 1992-03-26 1994-08-23 Nec Corporation Dynamic random access memory device having addressing section and/or data transferring path arranged in pipeline architecture
KR100239718B1 (en) * 1996-12-31 2000-01-15 김영환 Write circuit of multi-port semiconductor device
KR100382669B1 (en) * 1994-06-06 2003-07-18 가부시키가이샤 히타치 쪼오 엘.에스.아이.시스템즈 Memory system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128088A (en) * 1985-11-28 1987-06-10 Nec Corp Memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128088A (en) * 1985-11-28 1987-06-10 Nec Corp Memory device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287327A (en) * 1990-11-20 1994-02-15 Oki Electric Industry Co., Ltd. Synchronous dynamic random access memory
US5339276A (en) * 1990-11-20 1994-08-16 Oki Electric Industry Co., Ltd. Synchronous dynamic random access memory
US5430688A (en) * 1990-11-20 1995-07-04 Oki Electric Industry Co., Ltd. Synchronous dynamic random access memory
US5521879A (en) * 1990-11-20 1996-05-28 Oki Electric Industry Co., Ltd. Synchronous dynamic random acess memory
US5341341A (en) * 1992-03-26 1994-08-23 Nec Corporation Dynamic random access memory device having addressing section and/or data transferring path arranged in pipeline architecture
KR100382669B1 (en) * 1994-06-06 2003-07-18 가부시키가이샤 히타치 쪼오 엘.에스.아이.시스템즈 Memory system
KR100239718B1 (en) * 1996-12-31 2000-01-15 김영환 Write circuit of multi-port semiconductor device

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