JPS6471356A - Multi-direction serial data communication equipment - Google Patents
Multi-direction serial data communication equipmentInfo
- Publication number
- JPS6471356A JPS6471356A JP62227927A JP22792787A JPS6471356A JP S6471356 A JPS6471356 A JP S6471356A JP 62227927 A JP62227927 A JP 62227927A JP 22792787 A JP22792787 A JP 22792787A JP S6471356 A JPS6471356 A JP S6471356A
- Authority
- JP
- Japan
- Prior art keywords
- data
- transmission
- bus
- judges
- data communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To attain sure data transmission/reception between system by setting a waiting time for each system for data transmission processing to prevent the transmission of data simultaneously to a BUS. CONSTITUTION:A microcomputer judges the input state of function key K1, K2 and input/output ports I/O. When the microcomputer judges the necessity of data transmission, the I/O is switched to an output and B1 of BUS data is sent to a management BUS B1 and data B2 is sent to a data BUS B2. The management BUS B1 uses different times from OFF to the start of transmission depending on systems A-C (t1<t2<t3). The system B, C monitor the BUS B1, B2 via each I/O at all times and take the transmission data of the system A in each RAM. When the taken-in data is effective data (9) of the system A set in advance, the transmission data (5) is set to the RAM. Similarly, the system C takes in the transmission data but the microcomputer CPU-C judges it as invalid data and does not set the transmission data.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62227927A JPS6471356A (en) | 1987-09-11 | 1987-09-11 | Multi-direction serial data communication equipment |
KR1019880011754A KR910005380B1 (en) | 1987-09-11 | 1988-09-12 | Multi-direction serial data communication equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62227927A JPS6471356A (en) | 1987-09-11 | 1987-09-11 | Multi-direction serial data communication equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6471356A true JPS6471356A (en) | 1989-03-16 |
Family
ID=16868474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62227927A Pending JPS6471356A (en) | 1987-09-11 | 1987-09-11 | Multi-direction serial data communication equipment |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS6471356A (en) |
KR (1) | KR910005380B1 (en) |
-
1987
- 1987-09-11 JP JP62227927A patent/JPS6471356A/en active Pending
-
1988
- 1988-09-12 KR KR1019880011754A patent/KR910005380B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR910005380B1 (en) | 1991-07-29 |
KR890005620A (en) | 1989-05-16 |
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