JPS56123191A - Inter-processor communication control system - Google Patents

Inter-processor communication control system

Info

Publication number
JPS56123191A
JPS56123191A JP2709880A JP2709880A JPS56123191A JP S56123191 A JPS56123191 A JP S56123191A JP 2709880 A JP2709880 A JP 2709880A JP 2709880 A JP2709880 A JP 2709880A JP S56123191 A JPS56123191 A JP S56123191A
Authority
JP
Japan
Prior art keywords
information
call processing
communication
processor
ipc3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2709880A
Other languages
Japanese (ja)
Other versions
JPS6259958B2 (en
Inventor
Tatsuo Nakada
Hironao Ozeki
Takeshi Kawasaki
Masato Suyama
Hidenao Munekata
Tadashi Koizumi
Akira Kusaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP2709880A priority Critical patent/JPS56123191A/en
Publication of JPS56123191A publication Critical patent/JPS56123191A/en
Publication of JPS6259958B2 publication Critical patent/JPS6259958B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558—Redundancy, stand-by

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To prevent the delay of call processing in a decentralized control type electronic switching system, by providing each processor with a means of distributing communication information to an information transfer device for transfer between in-use and stand-by processors. CONSTITUTION:Each processor has a communication mode flag controllable by itself and another processor and, according to this information, distributes communication information to information transfer devices (IPC) 3-0 and 3-1 for transfer between in-use and stand-by processors. In normal call processing, the communication mode flag of each processor is set in normal mode and those pieces of call processing information are transmitted via in-use IPC3-0. In case of communication for a great amount of information except the call processing information, stand-by IPC3-1 performs the communication for the information except the call processing one and at the same time, in-use IPC3-0 performs that for the call processing information, thereby preventing the delay of the call processing.
JP2709880A 1980-03-04 1980-03-04 Inter-processor communication control system Granted JPS56123191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2709880A JPS56123191A (en) 1980-03-04 1980-03-04 Inter-processor communication control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2709880A JPS56123191A (en) 1980-03-04 1980-03-04 Inter-processor communication control system

Publications (2)

Publication Number Publication Date
JPS56123191A true JPS56123191A (en) 1981-09-28
JPS6259958B2 JPS6259958B2 (en) 1987-12-14

Family

ID=12211602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2709880A Granted JPS56123191A (en) 1980-03-04 1980-03-04 Inter-processor communication control system

Country Status (1)

Country Link
JP (1) JPS56123191A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01120987A (en) * 1987-10-08 1989-05-12 Northern Telecom Ltd System and method for parallel message transmission

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01120987A (en) * 1987-10-08 1989-05-12 Northern Telecom Ltd System and method for parallel message transmission

Also Published As

Publication number Publication date
JPS6259958B2 (en) 1987-12-14

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