JPS6471316A - Pulse reception circuit - Google Patents

Pulse reception circuit

Info

Publication number
JPS6471316A
JPS6471316A JP62228081A JP22808187A JPS6471316A JP S6471316 A JPS6471316 A JP S6471316A JP 62228081 A JP62228081 A JP 62228081A JP 22808187 A JP22808187 A JP 22808187A JP S6471316 A JPS6471316 A JP S6471316A
Authority
JP
Japan
Prior art keywords
output
circuit
pulse
output signal
leading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62228081A
Other languages
Japanese (ja)
Inventor
Tomohiro Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62228081A priority Critical patent/JPS6471316A/en
Publication of JPS6471316A publication Critical patent/JPS6471316A/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To make the output pulse width stable without the effect of input pulse amplitude fluctuation, by deciding an output pulse width in the leading edge and trailing edge of the retarded pulse without direct use of an output waveform of an LPF. CONSTITUTION:A pulse signal 102 superimposed with an impulse noise is inputted to an input terminal 2, it is compared with an output voltage 101 of a reference voltage generating circuit 1 by a comparator 3 and its output signal 103 is compared with a reference voltage 101 by a comparator 5 via an LPF 4. The output signal 105 and the output signal 106 of the pulse delay circuit 6 are ANDed by all AND circuit 108 and a differentiation circuit 8 detects the leading of the AND. On the other hand, the output signals 105, 106 are NORed by a NOR circuit 9 and a differentiation circuit 10 detects the leading. The output signals of the circuits 8, 10 are given to S, R terminals of the R-S FF and an output signal 111 without impulse noise is outputted from the output terminal 12.
JP62228081A 1987-09-11 1987-09-11 Pulse reception circuit Pending JPS6471316A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62228081A JPS6471316A (en) 1987-09-11 1987-09-11 Pulse reception circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62228081A JPS6471316A (en) 1987-09-11 1987-09-11 Pulse reception circuit

Publications (1)

Publication Number Publication Date
JPS6471316A true JPS6471316A (en) 1989-03-16

Family

ID=16870893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62228081A Pending JPS6471316A (en) 1987-09-11 1987-09-11 Pulse reception circuit

Country Status (1)

Country Link
JP (1) JPS6471316A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2296306A2 (en) 2009-09-15 2011-03-16 Yokogawa Electric Corporation Timing detection device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2296306A2 (en) 2009-09-15 2011-03-16 Yokogawa Electric Corporation Timing detection device
US8531177B2 (en) 2009-09-15 2013-09-10 Yokogawa Electric Corporation Timing detection device

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