JPS6467678A - Vector processor - Google Patents

Vector processor

Info

Publication number
JPS6467678A
JPS6467678A JP22559487A JP22559487A JPS6467678A JP S6467678 A JPS6467678 A JP S6467678A JP 22559487 A JP22559487 A JP 22559487A JP 22559487 A JP22559487 A JP 22559487A JP S6467678 A JPS6467678 A JP S6467678A
Authority
JP
Japan
Prior art keywords
subtracting
multiplying
data bus
pipe line
vector processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22559487A
Other languages
Japanese (ja)
Inventor
Satoru Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22559487A priority Critical patent/JPS6467678A/en
Publication of JPS6467678A publication Critical patent/JPS6467678A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain either of a multiplying and an adding and subtracting or the composite operation of the multiplying and the adding and subtracting with executing the switching control of a data bus and to increase the simultaneous parallel processing function of the adding and subtracting by sharing the data bus with a multiplying pipe line and providing an adding and subtracting pipe line. CONSTITUTION:To a multiplying pipe line 22a to be one of operating pipe lines, a multiplying and adding and subtracting pipe line 22 is provided to an adding and subtracting pipe line 22b without adding the data bus to an interval with a vector resistor 21. Since the switching control for the multiplying, for the adding and subtracting or of the data bus is executed as needed, the titled device can be used also for the composite operation of the multiplying and the adding and subtracting. Thus, without changing data bus constitution and data supplying control in a vector processor, the simultaneous parallel processing function of the adding and subtracting is improved.
JP22559487A 1987-09-09 1987-09-09 Vector processor Pending JPS6467678A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22559487A JPS6467678A (en) 1987-09-09 1987-09-09 Vector processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22559487A JPS6467678A (en) 1987-09-09 1987-09-09 Vector processor

Publications (1)

Publication Number Publication Date
JPS6467678A true JPS6467678A (en) 1989-03-14

Family

ID=16831766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22559487A Pending JPS6467678A (en) 1987-09-09 1987-09-09 Vector processor

Country Status (1)

Country Link
JP (1) JPS6467678A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0476772A (en) * 1990-07-18 1992-03-11 Hitachi Ltd Vector data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0476772A (en) * 1990-07-18 1992-03-11 Hitachi Ltd Vector data processor

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