JPS6466973A - Preparation of field effect transistor - Google Patents

Abstract

PURPOSE:To make it possible to manufacture a field effect transistor having large mutual conductance and capable of operating at high speed with good repeatability, by selectively growing an N-type semiconductor layer by an MOCVD method using an insulating side wall and a gate electrode as a mask and then etching it such that it becomes partially thin. CONSTITUTION:An undoped GaAs layer 3, an N<+> AlGaAs layer 2 and an undoped GaAs layer 1 are sequentially superposed on a semi-insulating GaAs substrate 4 and a gate electrode 5 is formed to form insulating side walls 6a and 6b comprising SiO2. An N<+> GaAs layer 7 is selectively grown by an MOCVD method using AsH3 and trimethylgalium and thinned by selectively etching the layer 7. Finally, an ohmic electrode (Au Ge) is provided on the thinned part to form a source electrode 8 and a drain electrode 9. Since the N<+> GaAs layer can be formed thickly, sheet resistance is decreased and since the part right beneath the source and drain electrodes is thin because of the etching, contact resistance can be reduced.