JPS6464237A - Forming method for multilayered interconnection in semiconductor device - Google Patents

Forming method for multilayered interconnection in semiconductor device

Info

Publication number
JPS6464237A
JPS6464237A JP22280087A JP22280087A JPS6464237A JP S6464237 A JPS6464237 A JP S6464237A JP 22280087 A JP22280087 A JP 22280087A JP 22280087 A JP22280087 A JP 22280087A JP S6464237 A JPS6464237 A JP S6464237A
Authority
JP
Japan
Prior art keywords
layer
wiring
pattern
inter
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22280087A
Other languages
Japanese (ja)
Other versions
JPH0680740B2 (en
Inventor
Tomoyuki Hikita
Katsutoshi Kura
Masaharu Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP22280087A priority Critical patent/JPH0680740B2/en
Publication of JPS6464237A publication Critical patent/JPS6464237A/en
Publication of JPH0680740B2 publication Critical patent/JPH0680740B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To prevent leakage among wirings by patterning a second wiring layer sputtered onto an inter-layer insulating film, using a resist pattern as a mask and etching the surface of the inter-layer insulating film by O2 plasma, employing the resist pattern and a second wiring pattern as masks. CONSTITUTION:Through-holes are bored to an inter-layer insulating film 10, a second wiring layer 12 is formed through a sputtering method, and a photo- resist pattern 13 is shaped onto a second wiring pattern region. The second wiring layer 12 is etched, using the pattern 13 as a mask to shape a second wiring pattern 12a. A desired quantity of a conductive modified layer 11 shaped at the time of the formation of the second wiring layer 12 on the surface of the inter-layer insulating film 10 is removed through O2 plasma etching, employing the photo-resist pattern 13 and the second wiring pattern 12a as masks. Accordingly, the conductive modified layer 13 among wirings in the layer 13 can be gotten rid of by O2 plasma, thus preventing leakage among the wirings.
JP22280087A 1987-09-03 1987-09-03 Method for forming multi-layer wiring of semiconductor device Expired - Lifetime JPH0680740B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22280087A JPH0680740B2 (en) 1987-09-03 1987-09-03 Method for forming multi-layer wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22280087A JPH0680740B2 (en) 1987-09-03 1987-09-03 Method for forming multi-layer wiring of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6464237A true JPS6464237A (en) 1989-03-10
JPH0680740B2 JPH0680740B2 (en) 1994-10-12

Family

ID=16788096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22280087A Expired - Lifetime JPH0680740B2 (en) 1987-09-03 1987-09-03 Method for forming multi-layer wiring of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0680740B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590426A (en) * 1991-09-27 1993-04-09 Nec Corp Manufacture of semiconductor device
WO2011089878A1 (en) 2010-01-19 2011-07-28 株式会社カネカ Curable composition
US8872040B2 (en) 2011-08-29 2014-10-28 Fujitsu Limited Wiring structure and manufacturing method thereof, and electronic apparatus and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590426A (en) * 1991-09-27 1993-04-09 Nec Corp Manufacture of semiconductor device
WO2011089878A1 (en) 2010-01-19 2011-07-28 株式会社カネカ Curable composition
US8872040B2 (en) 2011-08-29 2014-10-28 Fujitsu Limited Wiring structure and manufacturing method thereof, and electronic apparatus and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0680740B2 (en) 1994-10-12

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term