JPS6461844A - Input/output controller - Google Patents
Input/output controllerInfo
- Publication number
- JPS6461844A JPS6461844A JP21781187A JP21781187A JPS6461844A JP S6461844 A JPS6461844 A JP S6461844A JP 21781187 A JP21781187 A JP 21781187A JP 21781187 A JP21781187 A JP 21781187A JP S6461844 A JPS6461844 A JP S6461844A
- Authority
- JP
- Japan
- Prior art keywords
- input
- processor
- output
- address
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To decrease the number of program steps of each processor which performs the input/output control, by using a channel adaptor to secure the correspondence between the subchannel address received from a channel and the corresponding processor. CONSTITUTION:A channel adaptor 4 compares a device address received from a channel 2 with a subchannel address corresponding to each processor via a comparator 21. Then a microprocessor 23 secures the correspondence between the coincident subchannel address and its corresponding processor. An input/ output instruction produced from each processor functions to store the input/ output address word transferred by said input/output instruction temporarily into an input/output address word register 25. Then the processor 23 decides whether the preceding input/output instruction is being executed or not. If so, the input/output instruction is held and the register 25 is read after said instruction is executed. Then the next input/output instruction is executed. Thus the number of program steps can be decreased for the input/output procedure of each processor 6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21781187A JPS6461844A (en) | 1987-09-02 | 1987-09-02 | Input/output controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21781187A JPS6461844A (en) | 1987-09-02 | 1987-09-02 | Input/output controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6461844A true JPS6461844A (en) | 1989-03-08 |
Family
ID=16710111
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21781187A Pending JPS6461844A (en) | 1987-09-02 | 1987-09-02 | Input/output controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6461844A (en) |
-
1987
- 1987-09-02 JP JP21781187A patent/JPS6461844A/en active Pending
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