JPS6457691A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6457691A
JPS6457691A JP62213088A JP21308887A JPS6457691A JP S6457691 A JPS6457691 A JP S6457691A JP 62213088 A JP62213088 A JP 62213088A JP 21308887 A JP21308887 A JP 21308887A JP S6457691 A JPS6457691 A JP S6457691A
Authority
JP
Japan
Prior art keywords
submount
sink
fixed
heat sink
fixing materials
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62213088A
Other languages
Japanese (ja)
Inventor
Hideo Tamura
Makoto Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Development and Engineering Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Device Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Device Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP62213088A priority Critical patent/JPS6457691A/en
Publication of JPS6457691A publication Critical patent/JPS6457691A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To make it enough to perform temperature rise and cooling only once in a semiconductor element mounting process, wherein a submount is used, and to make it possible to realize a high-mounting position accuracy and highly reliable mounting, by a method wherein fixing material is formed in advance on both sides of the submount, and the element, the submount and a heat sink are fusion bonded simultaneously. CONSTITUTION:In case a semiconductor element 12 is fixed on a heat sink 11 through a submount 9 to manufacture a semiconductor device, fixing materials 5 consisting of the same kind of a material are respectively ready-formed in advance on both surfaces of a surface, on which the element 12 is fixed, of the submount 9, and a surface, which is fixed on the sink 1, of the submount 9. Moreover, after the above submount 9 and the element 12 are respectively arranged on the sink 1 and the submount 9, the element, the submount and the heat sink are heated at the melting point or more of the fixing materials and after that, are cooled. Thereby, the element 2 and the submount 9 are each mounted simultaneously on the submount 9 and the sink 1. For example, a Ti layer and a Pt layer are each formed on both surfaces of the submount 9 consisting of Si as electrode layers 7 and Au-Ge layers, which are used as the fixing materials 5, are each formed on the surfaces of both electrode layers 7 by vacuum deposition.
JP62213088A 1987-08-28 1987-08-28 Manufacture of semiconductor device Pending JPS6457691A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62213088A JPS6457691A (en) 1987-08-28 1987-08-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62213088A JPS6457691A (en) 1987-08-28 1987-08-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6457691A true JPS6457691A (en) 1989-03-03

Family

ID=16633357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62213088A Pending JPS6457691A (en) 1987-08-28 1987-08-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6457691A (en)

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