JPS6457541U - - Google Patents

Info

Publication number
JPS6457541U
JPS6457541U JP15301187U JP15301187U JPS6457541U JP S6457541 U JPS6457541 U JP S6457541U JP 15301187 U JP15301187 U JP 15301187U JP 15301187 U JP15301187 U JP 15301187U JP S6457541 U JPS6457541 U JP S6457541U
Authority
JP
Japan
Prior art keywords
input
output terminals
package
mpu
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15301187U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15301187U priority Critical patent/JPS6457541U/ja
Publication of JPS6457541U publication Critical patent/JPS6457541U/ja
Pending legal-status Critical Current

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  • Microcomputers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この考案のシングルチツプMPU装
置を例示した回路ブロツク図である。 1……CPU部、2……インターフエイスバス
、3……外部接続ピン、4……ピンセレクタ回路
、5……セレクト出力、6……クロツク/X′T
AL、7……リセツト。
FIG. 1 is a circuit block diagram illustrating a single-chip MPU device of this invention. 1...CPU section, 2...Interface bus, 3...External connection pin, 4...Pin selector circuit, 5...Select output, 6...Clock/X'T
AL, 7...Reset.

Claims (1)

【実用新案登録請求の範囲】 (1) シングルチツプMPUの入出力信号とパツ
ケージの入出力端子との間にピンセレクタ回路を
配し、パツケージの入出力端子の選択をMPU部
のフアームウエアで行うことを特徴とする入出力
端子数を少なくしたシングルチツプMPU装置。 (2) パツケージの入出力端子数を16ピン以下
とした実用新案登録請求の範囲第(1)項記載のシ
ングルチツプMPU装置。
[Claims for Utility Model Registration] (1) A pin selector circuit is arranged between the input/output signals of the single-chip MPU and the input/output terminals of the package, and the selection of the input/output terminals of the package is performed by the firmware of the MPU section. A single-chip MPU device with a reduced number of input/output terminals. (2) The single-chip MPU device according to claim (1) of the utility model registration claim, in which the number of input/output terminals of the package is 16 pins or less.
JP15301187U 1987-10-06 1987-10-06 Pending JPS6457541U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15301187U JPS6457541U (en) 1987-10-06 1987-10-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15301187U JPS6457541U (en) 1987-10-06 1987-10-06

Publications (1)

Publication Number Publication Date
JPS6457541U true JPS6457541U (en) 1989-04-10

Family

ID=31428463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15301187U Pending JPS6457541U (en) 1987-10-06 1987-10-06

Country Status (1)

Country Link
JP (1) JPS6457541U (en)

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