JPS6457332A - Squaring device - Google Patents
Squaring deviceInfo
- Publication number
- JPS6457332A JPS6457332A JP62213351A JP21335187A JPS6457332A JP S6457332 A JPS6457332 A JP S6457332A JP 62213351 A JP62213351 A JP 62213351A JP 21335187 A JP21335187 A JP 21335187A JP S6457332 A JPS6457332 A JP S6457332A
- Authority
- JP
- Japan
- Prior art keywords
- value
- supplied
- bits
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To reduce the whole circuit size by dividing an input signal into upper bits and lower bits and executing operation. CONSTITUTION:An inputted digital value X consisting of n bits is divided into a value A consisting of upper m1 bits and a value B consisting of lower m2 bits. The upper value A and the lower value B of the digital value X supplied to an input register 1 are respectively supplied to ROMs 2, 3 for executing squaring operation and both the values A, B are supplied to a multiplier 4. The output value A<2> of the ROM 2 is supplied to a 2<2m2> shifting circuit 5 and the output value A.B of the multiplier 4 is supplied to a 2<m2+1> shifting circuit 6. The output value A<2>.2<2m2> of the circuit 5, the output value 2AB.2<m2> of the circuit 6 and the output value B<2> of the ROM 3 are supplied to an adder 7 and the added value of these inputs is outputted to an output register 8 and X<2>.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62213351A JP2550597B2 (en) | 1987-08-27 | 1987-08-27 | Squarer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62213351A JP2550597B2 (en) | 1987-08-27 | 1987-08-27 | Squarer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6457332A true JPS6457332A (en) | 1989-03-03 |
JP2550597B2 JP2550597B2 (en) | 1996-11-06 |
Family
ID=16637724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62213351A Expired - Fee Related JP2550597B2 (en) | 1987-08-27 | 1987-08-27 | Squarer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2550597B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02191030A (en) * | 1989-01-20 | 1990-07-26 | Nec Corp | Square operation method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56143052A (en) * | 1980-03-17 | 1981-11-07 | Rockwell International Corp | Parallel digital arithmetic unit using rom |
JPS62147526A (en) * | 1985-12-23 | 1987-07-01 | Nec Corp | Multiplier |
-
1987
- 1987-08-27 JP JP62213351A patent/JP2550597B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56143052A (en) * | 1980-03-17 | 1981-11-07 | Rockwell International Corp | Parallel digital arithmetic unit using rom |
JPS62147526A (en) * | 1985-12-23 | 1987-07-01 | Nec Corp | Multiplier |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02191030A (en) * | 1989-01-20 | 1990-07-26 | Nec Corp | Square operation method |
Also Published As
Publication number | Publication date |
---|---|
JP2550597B2 (en) | 1996-11-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |