JPS6457332A - Squaring device - Google Patents

Squaring device

Info

Publication number
JPS6457332A
JPS6457332A JP62213351A JP21335187A JPS6457332A JP S6457332 A JPS6457332 A JP S6457332A JP 62213351 A JP62213351 A JP 62213351A JP 21335187 A JP21335187 A JP 21335187A JP S6457332 A JPS6457332 A JP S6457332A
Authority
JP
Japan
Prior art keywords
value
supplied
bits
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62213351A
Other languages
Japanese (ja)
Other versions
JP2550597B2 (en
Inventor
Takao Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62213351A priority Critical patent/JP2550597B2/en
Publication of JPS6457332A publication Critical patent/JPS6457332A/en
Application granted granted Critical
Publication of JP2550597B2 publication Critical patent/JP2550597B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the whole circuit size by dividing an input signal into upper bits and lower bits and executing operation. CONSTITUTION:An inputted digital value X consisting of n bits is divided into a value A consisting of upper m1 bits and a value B consisting of lower m2 bits. The upper value A and the lower value B of the digital value X supplied to an input register 1 are respectively supplied to ROMs 2, 3 for executing squaring operation and both the values A, B are supplied to a multiplier 4. The output value A<2> of the ROM 2 is supplied to a 2<2m2> shifting circuit 5 and the output value A.B of the multiplier 4 is supplied to a 2<m2+1> shifting circuit 6. The output value A<2>.2<2m2> of the circuit 5, the output value 2AB.2<m2> of the circuit 6 and the output value B<2> of the ROM 3 are supplied to an adder 7 and the added value of these inputs is outputted to an output register 8 and X<2>.
JP62213351A 1987-08-27 1987-08-27 Squarer Expired - Fee Related JP2550597B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62213351A JP2550597B2 (en) 1987-08-27 1987-08-27 Squarer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62213351A JP2550597B2 (en) 1987-08-27 1987-08-27 Squarer

Publications (2)

Publication Number Publication Date
JPS6457332A true JPS6457332A (en) 1989-03-03
JP2550597B2 JP2550597B2 (en) 1996-11-06

Family

ID=16637724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62213351A Expired - Fee Related JP2550597B2 (en) 1987-08-27 1987-08-27 Squarer

Country Status (1)

Country Link
JP (1) JP2550597B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02191030A (en) * 1989-01-20 1990-07-26 Nec Corp Square operation method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56143052A (en) * 1980-03-17 1981-11-07 Rockwell International Corp Parallel digital arithmetic unit using rom
JPS62147526A (en) * 1985-12-23 1987-07-01 Nec Corp Multiplier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56143052A (en) * 1980-03-17 1981-11-07 Rockwell International Corp Parallel digital arithmetic unit using rom
JPS62147526A (en) * 1985-12-23 1987-07-01 Nec Corp Multiplier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02191030A (en) * 1989-01-20 1990-07-26 Nec Corp Square operation method

Also Published As

Publication number Publication date
JP2550597B2 (en) 1996-11-06

Similar Documents

Publication Publication Date Title
JPS5421152A (en) Comparison circuit
JPS5340257A (en) Tone control circuit
JPS5243308A (en) Signal transmitting system
JPS535520A (en) Facsimile transmitter
JPS6457332A (en) Squaring device
JPS5311A (en) S/n ratio enhancing unit
JPS5441651A (en) Digital filter of non-circulation type
JPS5666947A (en) Data transmission method
JPS5374022A (en) Sound volume envelop setting system in electronic musical instrument
JPS6472230A (en) Bit inverter
JPS6484333A (en) Divider
JPS5518706A (en) Parallel adder circuit
JPS6486271A (en) Accumulator
JPS5666977A (en) Picture gradation property conversion device
JPS53140482A (en) Signal limiting circuit
JPS5651180A (en) Video signal binary device
JPS5546658A (en) Digital phase shifter
JPS5422140A (en) Digital differential analyzer
JPS6442733A (en) Adder using 2m-a as modulus
JPS5510688A (en) Control circuit
JPS5374449A (en) Two-wire type signal converter
JPS547841A (en) Variable frequency oscillator
JPS5494856A (en) Non-circulation type filter
JPS5572256A (en) Information processor
JPS5435720A (en) Sound source circuit

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees