JPS6454797A - Multilayer interconnection substrate - Google Patents

Multilayer interconnection substrate

Info

Publication number
JPS6454797A
JPS6454797A JP21004987A JP21004987A JPS6454797A JP S6454797 A JPS6454797 A JP S6454797A JP 21004987 A JP21004987 A JP 21004987A JP 21004987 A JP21004987 A JP 21004987A JP S6454797 A JPS6454797 A JP S6454797A
Authority
JP
Japan
Prior art keywords
film
substrate
insulating layer
multilayer interconnection
interconnection substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21004987A
Other languages
Japanese (ja)
Inventor
Akira Murata
Yasunori Narizuka
Mitsuru Usui
Minoru Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP21004987A priority Critical patent/JPS6454797A/en
Publication of JPS6454797A publication Critical patent/JPS6454797A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve the solderability of a connecting terminal and to obtain an integrated circuit multilayer interconnection substrate adapted for transmitting a high speed signal by forming part or all of soldering electrode terminals formed on an organic insulating layer of the substrate for forming an electric circuit with a nickel-copper alloy. CONSTITUTION:A polyimide surface insulating layer 4 having through holes 3 is formed on the top of wirings 2 made or Cu for connecting to a soldering terminal on the substrate 1 made of multilayer circuit substrate or ceramics having an insulating layer made of organic material. Then, a Cr film 51 is formed in a predetermined thickness by a method, such as vacuum depositing or sputtering, and an Ni-Cu alloy film 52 is formed in a predetermined thickness. After the film forming step is finished, a desired soldering terminal 6 is formed by photoetching. Cupric iodide or chloride solution is used to etch the film 52 at this time, caustic potash solution is used for the film 51 to obtain a multilayer interconnection substrate to be soldered in high reliability and repetition.
JP21004987A 1987-08-26 1987-08-26 Multilayer interconnection substrate Pending JPS6454797A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21004987A JPS6454797A (en) 1987-08-26 1987-08-26 Multilayer interconnection substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21004987A JPS6454797A (en) 1987-08-26 1987-08-26 Multilayer interconnection substrate

Publications (1)

Publication Number Publication Date
JPS6454797A true JPS6454797A (en) 1989-03-02

Family

ID=16582957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21004987A Pending JPS6454797A (en) 1987-08-26 1987-08-26 Multilayer interconnection substrate

Country Status (1)

Country Link
JP (1) JPS6454797A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4132995A1 (en) * 1991-10-04 1993-04-08 Bodenseewerk Geraetetech METHOD FOR PRODUCING ELECTRICALLY CONDUCTIVE CONNECTIONS ON PCB
US5523920A (en) * 1994-01-03 1996-06-04 Motorola, Inc. Printed circuit board comprising elevated bond pads
US20190283190A1 (en) * 2018-03-19 2019-09-19 Asia Vital Components Co., Ltd. Soldering method of soldering jig

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4132995A1 (en) * 1991-10-04 1993-04-08 Bodenseewerk Geraetetech METHOD FOR PRODUCING ELECTRICALLY CONDUCTIVE CONNECTIONS ON PCB
US5523920A (en) * 1994-01-03 1996-06-04 Motorola, Inc. Printed circuit board comprising elevated bond pads
US20190283190A1 (en) * 2018-03-19 2019-09-19 Asia Vital Components Co., Ltd. Soldering method of soldering jig
US10695875B2 (en) * 2018-03-19 2020-06-30 Asia Vital Components Co., Ltd. Soldering method of soldering jig

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