JPS6454563A - Input/output controller - Google Patents

Input/output controller

Info

Publication number
JPS6454563A
JPS6454563A JP21164987A JP21164987A JPS6454563A JP S6454563 A JPS6454563 A JP S6454563A JP 21164987 A JP21164987 A JP 21164987A JP 21164987 A JP21164987 A JP 21164987A JP S6454563 A JPS6454563 A JP S6454563A
Authority
JP
Japan
Prior art keywords
counter
address
register
output
dma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21164987A
Other languages
Japanese (ja)
Inventor
Takanori Umeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21164987A priority Critical patent/JPS6454563A/en
Publication of JPS6454563A publication Critical patent/JPS6454563A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To detect a malfunction of a DMA circuit in an early stage, and to prevent the disturbance of an output data or a fault such as a memory breakdown, by providing a means for comparing the output of an address register with the output of an address counter. CONSTITUTION:A data transfer start address and the number of data transfer words instructed by a CPU 1 are set to an address register 8 and a range register 9, thereafter, transferred to an address counter 10 and a range counter 11, and a DMA control circuit 12 is started. Subsequently, a data stored in a memory address of a main storage device 2 shown by the counter 10 is outputted to an I/O 4 through an input/output buffer 15, thereafter, the contents of the counter 10 are updated and the following data is read out of the device 2. Simultaneously, the register 8 is updated, outputs of the register 8 and the counter 10 are compared by a comparator 14, and when the discrepancy is detected, the DMA transfer is suspended against the circuit 12, and it is informed to the CPU 1. In such a way, the malfunction of a DMA circuit 13 is detected in the early stage and the generated of a system fault can be prevented.
JP21164987A 1987-08-26 1987-08-26 Input/output controller Pending JPS6454563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21164987A JPS6454563A (en) 1987-08-26 1987-08-26 Input/output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21164987A JPS6454563A (en) 1987-08-26 1987-08-26 Input/output controller

Publications (1)

Publication Number Publication Date
JPS6454563A true JPS6454563A (en) 1989-03-02

Family

ID=16609286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21164987A Pending JPS6454563A (en) 1987-08-26 1987-08-26 Input/output controller

Country Status (1)

Country Link
JP (1) JPS6454563A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545698B2 (en) * 2000-12-29 2003-04-08 Samsung Electronics, Co., Ltd. Mobile video telephone with automatic answering function and method for controlling the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545698B2 (en) * 2000-12-29 2003-04-08 Samsung Electronics, Co., Ltd. Mobile video telephone with automatic answering function and method for controlling the same

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