JPS6454552A - Data transfer system - Google Patents
Data transfer systemInfo
- Publication number
- JPS6454552A JPS6454552A JP21013787A JP21013787A JPS6454552A JP S6454552 A JPS6454552 A JP S6454552A JP 21013787 A JP21013787 A JP 21013787A JP 21013787 A JP21013787 A JP 21013787A JP S6454552 A JPS6454552 A JP S6454552A
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- register
- address
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To transfer a data at a high speed between a built-in register of a processor and a memory, even when an address of a byte unit does not coincide, by providing a data latch and a selector on a bus between a microprocessor and the memory. CONSTITUTION:In case of transferring a data by a word unit between a memory 4 in which one word is constituted of N (N is an integer of >=2) bytes, and a built-in register 6 of a microprocessor 1, a data latch and a selector are provided on a bus between the processor 1 and the memory 4. That is, registers 15-18 for latching a data of one byte, and selectors 19, 20 for outputting selectively an input or output data of each register are provided by a byte unit. In this state, when an address of the register corresponding to the data to be transferred and an address of the memory 4 coincide by a byte unit, an output of each selector goes to an input side of each data latch, and in case of discrepancy, said output becomes an output side. In such a way, even when the address of the byte unit does not coincide, the data can be transferred at a high speed between the register 6 and the memory 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21013787A JPS6454552A (en) | 1987-08-26 | 1987-08-26 | Data transfer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21013787A JPS6454552A (en) | 1987-08-26 | 1987-08-26 | Data transfer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6454552A true JPS6454552A (en) | 1989-03-02 |
Family
ID=16584394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21013787A Pending JPS6454552A (en) | 1987-08-26 | 1987-08-26 | Data transfer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6454552A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006481A (en) * | 1989-11-30 | 1991-04-09 | Sgs-Thomson Microelectronics, Inc. | Method of making a stacked capacitor DRAM cell |
US5787240A (en) * | 1994-05-20 | 1998-07-28 | Fujitsu Ltd. | Printer control apparatus converting video data from an external host to video data for a printer |
-
1987
- 1987-08-26 JP JP21013787A patent/JPS6454552A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006481A (en) * | 1989-11-30 | 1991-04-09 | Sgs-Thomson Microelectronics, Inc. | Method of making a stacked capacitor DRAM cell |
US5787240A (en) * | 1994-05-20 | 1998-07-28 | Fujitsu Ltd. | Printer control apparatus converting video data from an external host to video data for a printer |
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