JPS6453630A - A/d converter - Google Patents

A/d converter

Info

Publication number
JPS6453630A
JPS6453630A JP21047987A JP21047987A JPS6453630A JP S6453630 A JPS6453630 A JP S6453630A JP 21047987 A JP21047987 A JP 21047987A JP 21047987 A JP21047987 A JP 21047987A JP S6453630 A JPS6453630 A JP S6453630A
Authority
JP
Japan
Prior art keywords
input
output
circuit
added
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21047987A
Other languages
Japanese (ja)
Inventor
Fumio Yasui
Takashi Nakatsuka
Mitsuharu Tsuchiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP21047987A priority Critical patent/JPS6453630A/en
Publication of JPS6453630A publication Critical patent/JPS6453630A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To attain the highly speedy A/D conversion by switching and outputting a digital signal outputted by a comparator with the output of a logical circuit when two input signals are A/D-converted with a time division. CONSTITUTION:An output current i1-1 generated by a D/A converting circuit 1 and an input current i2-1 when an input signal V1 flows at an input resistance 4-1 are added at a comparator circuit 2-1 and compared with a ground potential. In the same way, an output current i1-2 and an input current i2-2 when an input signal V2 flows at a resistance 4-2 are added and compared with a ground potential. The output of comparators 2-1 and 2-2 is added to AND circuits 7-1 and 7-2 together with timing signals T1 and T2, the OR of the output is obtained by the circuit 8 and inputted into an successive approximate register 3. Bits 1-n of the D/A converting circuit 1 are converted and sent to a serial signal by a clock signal. Thus, an A/D conversion is made highly speedy.
JP21047987A 1987-08-25 1987-08-25 A/d converter Pending JPS6453630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21047987A JPS6453630A (en) 1987-08-25 1987-08-25 A/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21047987A JPS6453630A (en) 1987-08-25 1987-08-25 A/d converter

Publications (1)

Publication Number Publication Date
JPS6453630A true JPS6453630A (en) 1989-03-01

Family

ID=16590025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21047987A Pending JPS6453630A (en) 1987-08-25 1987-08-25 A/d converter

Country Status (1)

Country Link
JP (1) JPS6453630A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583503A (en) * 1993-10-06 1996-12-10 Mitsubishi Denki Kabushiki Kaisha Analog/digital converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583503A (en) * 1993-10-06 1996-12-10 Mitsubishi Denki Kabushiki Kaisha Analog/digital converter

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