JPS6450565A - Mos semiconductor integrated circuit device and manufacture thereof - Google Patents
Mos semiconductor integrated circuit device and manufacture thereofInfo
- Publication number
- JPS6450565A JPS6450565A JP20772687A JP20772687A JPS6450565A JP S6450565 A JPS6450565 A JP S6450565A JP 20772687 A JP20772687 A JP 20772687A JP 20772687 A JP20772687 A JP 20772687A JP S6450565 A JPS6450565 A JP S6450565A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- side face
- polysilicide
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To prevent the scattering of impurities into polycrystalline silicon while the annealing for lowering of the resistance of a polysilicide wiring is bending conducted, and also to prevent the fluctuation and variability of work function and Vth by a method wherein a thermally oxided film is formed on the surface and the side face of the polyside wiring consisting of a P<+>-doped polycrystalline silicon layer and a silicide layer. CONSTITUTION:In the MOS semiconductor integrated circuit device having the MOS field effect transistor wherein the polysilicide structure wiring consisting of a P<+>-doped polycrystalline silicon layer 5 is used as a gate electrode, a thermally oxided film 6 is formed on the surface and the side face of said silicon layer 5 and also on the side face of the polycrystalline silicon layer 4. For example, a polycrystalline silicon layer 4 is formed, boron is thermally diffused from above the layer 4, and the layer 4 is formed into P<+> type. After a silicide layer 5 has been formed thereon, a polysilicide wiring, a polysilicide gate and the like are formed by conducting selective etching. Then, an oxide film 6 is formed on the surface and the side face of the silicide layer 5 and on the side face of the polycrystalline silicon 4 by conducting light oxidation. Then, a heat treatment is conducted for the purpose of lowering the resistance of the silicide layer 5.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20772687A JPS6450565A (en) | 1987-08-21 | 1987-08-21 | Mos semiconductor integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20772687A JPS6450565A (en) | 1987-08-21 | 1987-08-21 | Mos semiconductor integrated circuit device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6450565A true JPS6450565A (en) | 1989-02-27 |
Family
ID=16544526
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20772687A Pending JPS6450565A (en) | 1987-08-21 | 1987-08-21 | Mos semiconductor integrated circuit device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6450565A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2010287341B2 (en) * | 2009-08-27 | 2014-05-22 | Commonwealth Scientific And Industrial Research Organisation | Hybrid negative plate for lead-acid storage battery and lead-acid storage battery |
-
1987
- 1987-08-21 JP JP20772687A patent/JPS6450565A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2010287341B2 (en) * | 2009-08-27 | 2014-05-22 | Commonwealth Scientific And Industrial Research Organisation | Hybrid negative plate for lead-acid storage battery and lead-acid storage battery |
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