JPS6450120A - Register file - Google Patents
Register fileInfo
- Publication number
- JPS6450120A JPS6450120A JP62206176A JP20617687A JPS6450120A JP S6450120 A JPS6450120 A JP S6450120A JP 62206176 A JP62206176 A JP 62206176A JP 20617687 A JP20617687 A JP 20617687A JP S6450120 A JPS6450120 A JP S6450120A
- Authority
- JP
- Japan
- Prior art keywords
- address
- circuit group
- write
- adder
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To decrease the hardware quantity, and also, to prevent the increase of a set-up time of a write address, by providing an address use sub-latching circuit and an address use main latching circuit having an address selector function. CONSTITUTION:In a register file which is stored temporarily a write address in an address use main latching circuit group 3, so that a data is written to a store position corresponding to this stored address, an address use sub-latching circuit group 12 is provided. In the circuit group 12, an output address of the circuit group 3 is stored, and to an output of the circuit group 3, '1' is added through an adder 11, and in response to a reset command signal, an input of the circuit group 3 is switched to an output of the adder 11 from the write address through a selector group 9, and in accordance with a reset instruction signal, the write data is supplied as '0'. In such a way, a value of the circuit group 3 is counted up through the circuit group 12 and the adder 11, whenever a reset signal is inputted, therefore, the hardware quantity is decreased and the increase of a set-up time of a write address can also be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62206176A JPS6450120A (en) | 1987-08-19 | 1987-08-19 | Register file |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62206176A JPS6450120A (en) | 1987-08-19 | 1987-08-19 | Register file |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6450120A true JPS6450120A (en) | 1989-02-27 |
Family
ID=16519069
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62206176A Pending JPS6450120A (en) | 1987-08-19 | 1987-08-19 | Register file |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6450120A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5503787A (en) * | 1993-03-11 | 1996-04-02 | Hitachi, Ltd. | Method for manufacturing multilayer ceramic substrate |
-
1987
- 1987-08-19 JP JP62206176A patent/JPS6450120A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5503787A (en) * | 1993-03-11 | 1996-04-02 | Hitachi, Ltd. | Method for manufacturing multilayer ceramic substrate |
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