JPS6447975A - Testing of integrated circuit - Google Patents

Testing of integrated circuit

Info

Publication number
JPS6447975A
JPS6447975A JP62204167A JP20416787A JPS6447975A JP S6447975 A JPS6447975 A JP S6447975A JP 62204167 A JP62204167 A JP 62204167A JP 20416787 A JP20416787 A JP 20416787A JP S6447975 A JPS6447975 A JP S6447975A
Authority
JP
Japan
Prior art keywords
terminal
clock
tested
terminals
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62204167A
Other languages
Japanese (ja)
Inventor
Hideaki Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62204167A priority Critical patent/JPS6447975A/en
Publication of JPS6447975A publication Critical patent/JPS6447975A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To enable the compression of a test pattern, by employing an FF within an IC which can be set in combination of signals unavailable in actual use to get tested or reset by combining an output of the FF and an input in no way affecting a portion as object to be tested. CONSTITUTION:A fixed time length '1' is applied to a terminal F for a fixed time and then, '0' to a circuit to initialize it. When the terminal F is down to '0', a signal is applied to terminals G and H to turn a line L6 to '1' through an FF9. Then, '0' is applied to a terminal B and '1' to terminals D and E. A clock input is applied to terminals A and C separately for a frequency dividing circuit 1 and a function block 4. Under such a condition, a clock input from the terminal C enters the block 4, an output of which can be observed directly at a terminal 1. Moreover, a clock route can be tested by applying '0' to the terminal D. In this case, before the applying of '0' to the terminal D, a signal input is given to the terminal B to initialize the circuit 1 thereby enabling compression of a test pattern with a phase matching in the switching of a clock.
JP62204167A 1987-08-19 1987-08-19 Testing of integrated circuit Pending JPS6447975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62204167A JPS6447975A (en) 1987-08-19 1987-08-19 Testing of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62204167A JPS6447975A (en) 1987-08-19 1987-08-19 Testing of integrated circuit

Publications (1)

Publication Number Publication Date
JPS6447975A true JPS6447975A (en) 1989-02-22

Family

ID=16485947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62204167A Pending JPS6447975A (en) 1987-08-19 1987-08-19 Testing of integrated circuit

Country Status (1)

Country Link
JP (1) JPS6447975A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9303603B2 (en) 2012-07-11 2016-04-05 Kawasaki Jukogyo Kabushiki Kaisha Air intake structure for vehicle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9303603B2 (en) 2012-07-11 2016-04-05 Kawasaki Jukogyo Kabushiki Kaisha Air intake structure for vehicle

Similar Documents

Publication Publication Date Title
KR960003991B1 (en) Testing circuit comprising integrated circuits provided on a carrier
MY130533A (en) Controllable and testable oscillator apparatus for an integrated circuit
EP0903755A3 (en) Ciruit and method to externally adjust internal circuit timing
JPS6447975A (en) Testing of integrated circuit
JPS5344135A (en) Function test equipment for logical operation circuit
FR2659144B2 (en) ELECTRONIC DEVICE FOR TESTING A NETWORK OF COMPONENTS, IN PARTICULAR AN ELECTRONIC CIRCUIT.
JPS5537924A (en) Integrated circuit
JPS5745942A (en) Semiconductor integrated circuit device
JPS5629177A (en) Semiconductor integrated circuit device
JPS57111714A (en) Integrated circuit
JPS575164A (en) Test input circuit of microcomputer
JPS53118327A (en) Automatic test data generator
JPS5651677A (en) Testing method
JPS6454380A (en) Electronic circuit package with automatic testing function
JPS6479674A (en) Method of testing integrated circuit
JPS5381084A (en) Testing method of integrated circuit
EP0898282A3 (en) Semiconductor integrated circuit and method for designing the same
JPS5745941A (en) Semiconductor integrated circuit device
JPS5593070A (en) Frequency decision circuit
TW350918B (en) Testing method and apparatus of a digital circuit
JPS6479670A (en) Test circuit generation system
KR970008085B1 (en) Test method for semiconductor
JPS5610721A (en) Amplitude limiting device
JPS5694648A (en) Digital ic
JPS5661663A (en) Testing device of logic circuit