JPS6447051A - Formation of multilayer interconnection - Google Patents

Formation of multilayer interconnection

Info

Publication number
JPS6447051A
JPS6447051A JP20579287A JP20579287A JPS6447051A JP S6447051 A JPS6447051 A JP S6447051A JP 20579287 A JP20579287 A JP 20579287A JP 20579287 A JP20579287 A JP 20579287A JP S6447051 A JPS6447051 A JP S6447051A
Authority
JP
Japan
Prior art keywords
wiring layer
aluminum
electrode wiring
contact hole
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20579287A
Other languages
Japanese (ja)
Inventor
Kenji Nishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20579287A priority Critical patent/JPS6447051A/en
Publication of JPS6447051A publication Critical patent/JPS6447051A/en
Pending legal-status Critical Current

Links

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form an electrode wiring layer excellent in a step coverage in a contact hole provided to an insulating film of a multilayer interconnection by a method wherein a first electrode wiring layer formed of aluminum is subjected to a heat treatment, where melted aluminum is made to ascend up in the contact hole through the fluidity and the expansion of the melted first electrode wiring layer and the stress occurred in a second insulating film provided to the first electrode wiring layer. CONSTITUTION:A first electrode wiring layer 3 of an aluminum wiring layer is provided to a first insulating film 2, for instance, a silicon nitride film formed on a silicon substrate 1 and a second insulating film 4 is formed thereon. Next, the silicon substrate 1 is heated, where the aluminum wiring layer is made to melt to expand, aluminum ascends up in a contact hole 4a through the pressure impressed through the difference in the thermal expansion coefficient between the silicon nitride film and aluminum, and an aspect ratio is made to be small. Even when the silicon substrate decreases in temperature, aluminum in the contact hole 4a is kept in the same condition as it is because aluminum is very small in volume as compared with the first electrode wiring layer 3. Therefore, the face of a formed second electrode wiring layer 5 is made to be flat, wherefore a flat passivation film 6 is able to be formed even in the position of the contact hole 4a.
JP20579287A 1987-08-18 1987-08-18 Formation of multilayer interconnection Pending JPS6447051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20579287A JPS6447051A (en) 1987-08-18 1987-08-18 Formation of multilayer interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20579287A JPS6447051A (en) 1987-08-18 1987-08-18 Formation of multilayer interconnection

Publications (1)

Publication Number Publication Date
JPS6447051A true JPS6447051A (en) 1989-02-21

Family

ID=16512756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20579287A Pending JPS6447051A (en) 1987-08-18 1987-08-18 Formation of multilayer interconnection

Country Status (1)

Country Link
JP (1) JPS6447051A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926736A (en) * 1996-10-30 1999-07-20 Stmicroelectronics, Inc. Low temperature aluminum reflow for multilevel metallization
JP2015153879A (en) * 2014-02-13 2015-08-24 セイコーインスツル株式会社 Semiconductor device manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926736A (en) * 1996-10-30 1999-07-20 Stmicroelectronics, Inc. Low temperature aluminum reflow for multilevel metallization
JP2015153879A (en) * 2014-02-13 2015-08-24 セイコーインスツル株式会社 Semiconductor device manufacturing method

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