JPS6446872A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6446872A
JPS6446872A JP62204446A JP20444687A JPS6446872A JP S6446872 A JPS6446872 A JP S6446872A JP 62204446 A JP62204446 A JP 62204446A JP 20444687 A JP20444687 A JP 20444687A JP S6446872 A JPS6446872 A JP S6446872A
Authority
JP
Japan
Prior art keywords
address
dimensional
processing
outputted
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62204446A
Other languages
Japanese (ja)
Inventor
Eiji Osaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62204446A priority Critical patent/JPS6446872A/en
Publication of JPS6446872A publication Critical patent/JPS6446872A/en
Pending legal-status Critical Current

Links

Landscapes

  • Image Processing (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To realize multi-dimensional arithmetic processing with no waste and at a high speed by securing such constitution where the 2-dimensional data can be produced with a switching operation carried out between X and Y addresses and the lambda axis data on each 2-dimensional data area in taken out for production of the 3-dimensional data just with addition of a prescribed value to the X address. CONSTITUTION:In an address generating circuit 16, a mode switch part 163 receives a command from a host CPU 11 and sends a switch signal to an address switch part 164 when fast Fourier transformation processing FFT is started for 1-dimension (X), 2-dimension (Y) and 3-dimension waveforms. Then the X and Y addresses are outputted as they are to the part 164 at the 1-dimensional FFT processing. The X and Y addresses are replaced with each other and outputted to the part 164 at 2-dimensional FFT conversion processing. At the 3-dimensional FFT conversion processing, the Y address is outputted as it is to the part 164 and at the same time the X address is sent to an adder 165 for production of an address (X+DELTAx). This address (X+DELTAx) is sent to a register 166. Thus it is possible to realize the multi-dimensional arithmetic processing with no waste and at a high speed.
JP62204446A 1987-08-18 1987-08-18 Data processor Pending JPS6446872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62204446A JPS6446872A (en) 1987-08-18 1987-08-18 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62204446A JPS6446872A (en) 1987-08-18 1987-08-18 Data processor

Publications (1)

Publication Number Publication Date
JPS6446872A true JPS6446872A (en) 1989-02-21

Family

ID=16490663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62204446A Pending JPS6446872A (en) 1987-08-18 1987-08-18 Data processor

Country Status (1)

Country Link
JP (1) JPS6446872A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1063645A (en) * 1996-08-27 1998-03-06 Tsuneaki Daishidou Three-dimensional fft device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1063645A (en) * 1996-08-27 1998-03-06 Tsuneaki Daishidou Three-dimensional fft device

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