JPS6444576A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To execute multiplication and accumulative addition by means of an extremely simple circuit constitution by simultaneously executing two operations, addition and multiplication, in a parallel type multiplier and feeding back the multiplied result again to said parallel type multiplier. CONSTITUTION:The parallel type multiplier 6 with an additional function simultaneously executes the multiplication of signals D(i)61, K(i)62 and the addition of a feedback signal 64 to the multiplied result and outputs the computed result 63. A clear signal 51 is inputted to a switching device 5 at a clock period (t) to turn an signal outputted from the device 5 to zero, D(t) and K(t) are inputted to the multiplier 6 and the multiplied result of the D(t) and K(t) is stored in the register 4. Then, the output of the register is inputted to the multiplier 6 as a signal 64 through the device 5 at a clock period (t+1), and D(t+1) and K(t+1) are also inputted to the multiplier 6 and the output of the multiplier 6 is stored in the register 4. Thus, the multiplied results are accumulatively added by repeating said operation.