JPS6444054A - Manufacture of hybrid integrated circuit substrate - Google Patents

Manufacture of hybrid integrated circuit substrate

Info

Publication number
JPS6444054A
JPS6444054A JP20049687A JP20049687A JPS6444054A JP S6444054 A JPS6444054 A JP S6444054A JP 20049687 A JP20049687 A JP 20049687A JP 20049687 A JP20049687 A JP 20049687A JP S6444054 A JPS6444054 A JP S6444054A
Authority
JP
Japan
Prior art keywords
melting point
solder
integrated circuit
hybrid integrated
circuit substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20049687A
Other languages
Japanese (ja)
Inventor
Yoshinobu Abe
Yukiharu Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tamura Corp
Original Assignee
Tamura Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tamura Corp filed Critical Tamura Corp
Priority to JP20049687A priority Critical patent/JPS6444054A/en
Publication of JPS6444054A publication Critical patent/JPS6444054A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits

Landscapes

  • Ceramic Products (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To manufacture a hybrid integrated circuit substrate having a preferable thermal conductivity by bonding a metallized metal layer to a metal plate by a brazing material having a higher melting point than that of a normal solder, and reflow-soldering an electronic component to a circuit face under a temperature condition of the melting point of the solder or above and the melting point of the brazing material or below. CONSTITUTION:A metal layer 16 is metallized on the other side face of a ceramic plate 11 formed with a circuit on one side face, and the layer 16 is bonded by brazing with a brazing material 18, such as tin having higher melting point than that of a solder 31. Then, an electronic component 32 is placed through the solder 31 on the circuit face of the plate 11, and the component 32 is reflow soldered onto the circuit face under temperature condition of the melting point of the solder 31 or above to the melting point of the material 18 or below. Thus, a hybrid integrated circuit substrate having preferable thermal conductivity can be manufactured, thereby manufacturing a hybrid integrated circuit substrate for generating large quantity of heat, such as a power semiconductor module substrate, etc.
JP20049687A 1987-08-11 1987-08-11 Manufacture of hybrid integrated circuit substrate Pending JPS6444054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20049687A JPS6444054A (en) 1987-08-11 1987-08-11 Manufacture of hybrid integrated circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20049687A JPS6444054A (en) 1987-08-11 1987-08-11 Manufacture of hybrid integrated circuit substrate

Publications (1)

Publication Number Publication Date
JPS6444054A true JPS6444054A (en) 1989-02-16

Family

ID=16425286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20049687A Pending JPS6444054A (en) 1987-08-11 1987-08-11 Manufacture of hybrid integrated circuit substrate

Country Status (1)

Country Link
JP (1) JPS6444054A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345628A (en) * 2000-06-02 2001-12-14 Mitsumi Electric Co Ltd Helical antenna and its manufacturing method, resonance frequency adjustment method
WO2013191288A1 (en) * 2012-06-21 2013-12-27 京セラ株式会社 Circuit board and electronic apparatus provided with same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345628A (en) * 2000-06-02 2001-12-14 Mitsumi Electric Co Ltd Helical antenna and its manufacturing method, resonance frequency adjustment method
WO2013191288A1 (en) * 2012-06-21 2013-12-27 京セラ株式会社 Circuit board and electronic apparatus provided with same
EP2866534A4 (en) * 2012-06-21 2016-01-20 Kyocera Corp Circuit board and electronic apparatus provided with same
JP5905962B2 (en) * 2012-06-21 2016-04-20 京セラ株式会社 Circuit board and electronic device having the same
US9980384B2 (en) 2012-06-21 2018-05-22 Kyocera Corporation Circuit board and electronic apparatus including the same

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