JPS644361B2 - - Google Patents
Info
- Publication number
- JPS644361B2 JPS644361B2 JP59010498A JP1049884A JPS644361B2 JP S644361 B2 JPS644361 B2 JP S644361B2 JP 59010498 A JP59010498 A JP 59010498A JP 1049884 A JP1049884 A JP 1049884A JP S644361 B2 JPS644361 B2 JP S644361B2
- Authority
- JP
- Japan
- Prior art keywords
- line
- conductor
- coplanar
- circuit
- slot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 description 7
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/12—Coupling devices having more than two ports
Landscapes
- Waveguides (AREA)
Description
【発明の詳細な説明】
この発明はマイクロ波回路として用いられ、共
平面線路で構成された共平面回路に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a coplanar circuit that is used as a microwave circuit and is composed of coplanar lines.
＜従来技術＞
従来の共平面線路を用いて構成した回路は第１
図に示すように誘電体基板１１の一面にマイクロ
ストリツプ線路１２が形成され、誘電体基板１１
の他面に互に連結されたスロツト線路１３，１４
が形成され、誘電体基板１１内に設けたスルーホ
ール内の導体１５によつてマイクロストリツプ線
路１２とスロツト線路１３，１４とが結合されて
いた。例えばポート１６からの入力波はマイクロ
ストリツプ線路１２を伝搬し、スルーホール内導
体１５によつてスロツト線路１３，１４の伝搬に
変換され、それぞれポート１７，１８から出力が
得られる。<Prior art> The circuit constructed using the conventional coplanar line is
As shown in the figure, a microstrip line 12 is formed on one surface of a dielectric substrate 11.
Slot lines 13 and 14 connected to each other on the other side
was formed, and the microstrip line 12 and the slot lines 13 and 14 were coupled by a conductor 15 in a through hole provided in the dielectric substrate 11. For example, an input wave from port 16 propagates through microstrip line 12, is converted into propagation through slot lines 13 and 14 by through-hole conductor 15, and outputs are obtained from ports 17 and 18, respectively.
誘電体基板１１のスルーホールは通常ドリルま
たはレーザ等により形成される。このため、高い
工作精度が要求され、製造コストが高くなる問題
がある。また、使用周波数が高くなつた場合スル
ーホール内導体１５の寄生素子により伝送特性が
劣化するため適用周波数には限界があつた。また
この構成を半導体基板上で形成するモノリシツク
集積回路に適用した場合、半導体基板の裏面に対
してもパターンを形成しなければならないため、
エツチング工程数の増加、裏面を用いることによ
る基板寸法の増加等によりモノリシツク化による
マイクロ波回路の経済化、小形化を実現すること
は難しい。 The through holes in the dielectric substrate 11 are usually formed using a drill, laser, or the like. For this reason, there is a problem that high machining accuracy is required and manufacturing cost increases. Furthermore, when the operating frequency becomes high, the transmission characteristics deteriorate due to the parasitic elements of the through-hole conductor 15, so there is a limit to the applicable frequency. Furthermore, when this configuration is applied to a monolithic integrated circuit formed on a semiconductor substrate, a pattern must also be formed on the back side of the semiconductor substrate.
It is difficult to realize economicalization and miniaturization of microwave circuits by making them monolithic due to the increase in the number of etching steps and the increase in substrate size due to the use of the back side.
＜発明の目的＞
この発明はこれらの欠点を除去するため半導体
基板上のみで回路を構成できる共平面回路を提供
することを目的とするものである。<Objective of the Invention> In order to eliminate these drawbacks, it is an object of the present invention to provide a coplanar circuit that can be constructed only on a semiconductor substrate.
＜実施例＞
第２図はこの発明の第１実施例を示し、半導体
基板２１の一面上に導体層が形成され、その導体
層に対し、スロツト線路２２，２３がほヾ延長す
るように形成され、そのスロツト線路２２，２３
の接続点と交差してコプレナー線路２４が形成さ
れ、コプレナー線路２４の中心導体２５はストリ
ツプ導体２６を通じてスロツト線路２２，２３の
接続部を通り、スロツト線路２２，２３を構成す
るコプレナー線路２４と反対側の導体層２７に接
続される。ストリツプ導体２６の幅は中心導体２
５の幅より狭くされ集中定数的な接続とされてこ
れら線路２２，２３と２４とのインピーダンス整
合がなされる。かつコプレナー線路２４の中心導
体２５及び両外導体２８，２９間のスロツト３
１，３２がストリツプ線路２６の両側縁に沿つて
延長してスロツト線路２２，２３に連結するよう
に溝３３，３４が形成される。このスロツト線路
２２，２３とコプレナー線路２４との結合部にお
いて導体２８，２９が連結片３５で連結され、連
結片３５とストリツプ線路２６及びその両側の溝
３３，３４の底との間に例えばSiO2のような絶
縁層３６が介在される。連結片３５とストリツプ
線路２５との対向面積はなるべく小さくしてこれ
ら間の静電容量が小さくなるようにされる。スロ
ツト線路２２，２３とコプレナー線路２４との各
結合部と反対の端はそれぞれ入出力ポート３７，
３８，３９とされる。<Embodiment> FIG. 2 shows a first embodiment of the present invention, in which a conductor layer is formed on one surface of a semiconductor substrate 21, and slot lines 22 and 23 are formed so as to substantially extend with respect to the conductor layer. and its slot lines 22, 23
A coplanar line 24 is formed by intersecting the connection point of the slot lines 22 and 23, and the center conductor 25 of the coplanar line 24 passes through the strip conductor 26 to the connection part of the slot lines 22 and 23, and is opposite to the coplanar line 24 that constitutes the slot lines 22 and 23. It is connected to the conductor layer 27 on the side. The width of the strip conductor 26 is the width of the center conductor 2
The width of the lines 22, 23 and 24 is made narrower than the line width 5, and the lines 22, 23 and 24 are connected in a lumped constant manner to achieve impedance matching. and the slot 3 between the center conductor 25 and both outer conductors 28 and 29 of the coplanar line 24.
Grooves 33 and 34 are formed such that grooves 1 and 32 extend along both side edges of the strip line 26 and are connected to the slot lines 22 and 23. The conductors 28 and 29 are connected by a connection piece 35 at the joint between the slot lines 22 and 23 and the coplanar line 24, and between the connection piece 35 and the bottom of the strip line 26 and the grooves 33 and 34 on both sides thereof, for example, SiO2 is connected. An insulating layer 36 such as 2 is interposed. The opposing area of the connecting piece 35 and the strip line 25 is made as small as possible so that the capacitance between them is reduced. The ends opposite to the joints between the slot lines 22 and 23 and the coplanar line 24 have input/output ports 37, respectively.
38, 39.
第３図は第２図の動作原理を線路の伝搬モード
を用いて説明するための図である。コプレナー線
路２４の伝搬モードの電界の方向８は中心導体２
５から外側接地導体２９の方向に向いており、両
側の接地導体の電位は零ポテンシヤルになつてい
る。そのため第３図に示すように両側の導体を接
地片３５を用いて接続しても伝搬モードへの影響
は無い。すなわちコプレナー線路からスロツト線
路への変換部はこの特性を利用している。スロツ
ト線路２２，２３の電界はそれぞれ１０，９で示
した方向となつている。スロツト線路２２，２３
の特性インピーダンスを適当に選択することによ
つて出力ポート３７，３８からは同振幅、同位相
の出力が得られる。 FIG. 3 is a diagram for explaining the operating principle of FIG. 2 using the propagation mode of the line. The direction 8 of the electric field of the propagation mode of the coplanar line 24 is the center conductor 2
5 toward the outer ground conductor 29, and the potential of the ground conductors on both sides is zero potential. Therefore, even if the conductors on both sides are connected using the grounding piece 35 as shown in FIG. 3, there is no effect on the propagation mode. In other words, the converter from a coplanar line to a slot line utilizes this characteristic. The electric fields of the slot lines 22 and 23 are in the directions indicated by 10 and 9, respectively. Slot lines 22, 23
By appropriately selecting the characteristic impedance of the output ports 37 and 38, outputs of the same amplitude and phase can be obtained from the output ports 37 and 38.
第４図に第２図の等価回路を示す。スロツト線
路２２，２３とコプレナー線路２４とが互に接続
される。この等価回路はコプレナー線路２４がス
ロツト線路２２，２３で並列分岐された構成にな
つている。ストリツプ線路２６、連結片３５の交
差部は半導体技術で用いられるエツチングで製作
され、高い精度でパターンを作ることができる。
また絶縁層３６の厚みは線路間の結合が最小とな
るように、即ちストリツプ線路２６と連結片３５
との容量結合が小さく、かつ不連続部による寄生
素子を最小となるように製作することができる。
従つてこの構成による回路は高い周波数帯に適用
可能であり、また半導体基板２１の片面のみを使
用しているため、片面のみのエツチングでパター
ンを製作でき、更にスロツト線路２２，２３とコ
プレナー線路２４との接続部を多層構造で構成し
ているため、回路の寸法を十分小さくできる。そ
のため回路の経済化、小形化を達成できるモノリ
シツク集積回路を高周波帯で実現できる利点があ
る。例えばハイブリツド集積回路の場合は精度は
数十μm〜数百μm程度であるが、半導体製造技術
（エツチング技術）では1μm以下の精度とするこ
とができる。 FIG. 4 shows an equivalent circuit of FIG. 2. Slot lines 22, 23 and coplanar line 24 are connected to each other. This equivalent circuit has a configuration in which a coplanar line 24 is branched in parallel by slot lines 22 and 23. The intersection of the strip line 26 and the connecting piece 35 is fabricated by etching, which is used in semiconductor technology, and a pattern can be created with high precision.
The thickness of the insulating layer 36 is set such that coupling between the lines is minimized, that is, between the strip line 26 and the connecting piece 35.
It can be manufactured so that the capacitive coupling with the discontinuous portion is small and the parasitic elements due to the discontinuous portion are minimized.
Therefore, the circuit with this configuration is applicable to a high frequency band, and since only one side of the semiconductor substrate 21 is used, a pattern can be manufactured by etching only one side. Since the connection part with the 2-pin is constructed with a multilayer structure, the dimensions of the circuit can be made sufficiently small. Therefore, there is an advantage that a monolithic integrated circuit that can achieve economical and compact circuits can be realized in a high frequency band. For example, in the case of a hybrid integrated circuit, the precision is on the order of tens of micrometers to several hundred micrometers, but with semiconductor manufacturing technology (etching technology), the precision can be less than 1 micrometer.
以上述べたように、この発明による共平面回路
は半導体基板上でコプレナー線路とスロツト線路
とを結合する回路を簡易な構成で、しかも高周波
特性が良く、エツチング工程のみで製作できる利
点がある。 As described above, the coplanar circuit according to the present invention has the advantage that the circuit for coupling a coplanar line and a slot line on a semiconductor substrate has a simple structure, has good high frequency characteristics, and can be manufactured using only an etching process.
＜効果＞
以上説明したように、この発明による共平面回
路は半導体基板上に構成され、共平面線路、すな
わちスロツト線路及びコプレナー線路間の結合回
路を機械工作なしでエツチング工程のみで製作で
き、更にパターン寸法もエツチング精度で規定で
きるため、寄生素子、線路間結合等を避けること
が可能であり、従つてマイクロ波、ミリ波回路の
小形化、経済化を達成するモノリシツク集積回路
として応用できる利点がある。<Effects> As explained above, the coplanar circuit according to the present invention is constructed on a semiconductor substrate, and the coplanar line, that is, the coupling circuit between the slot line and the coplanar line can be fabricated only by an etching process without any mechanical work. Since the pattern dimensions can be defined with etching precision, it is possible to avoid parasitic elements, coupling between lines, etc., and therefore it has the advantage of being applicable as a monolithic integrated circuit that can achieve miniaturization and economicalization of microwave and millimeter wave circuits. be.
第１図は従来の共平面回路を示す斜視図、第２
図はこの発明の実施例を示す斜視図、第３図は動
作原理を説明するための図、第４図はその等価回
路図である。
８，９，１０：電界の方向、２１：半導体基
板、２２，２３：スロツト線路、２４：コプレナ
ー線路、２５：コプレナー線路の中心導体、２
６：ストリツプ導体、３５：絶縁層上ストリツプ
導体よりなる連結片、３６：絶縁層、３７，３
８，３９：入出力ポート。
Figure 1 is a perspective view showing a conventional coplanar circuit;
The figure is a perspective view showing an embodiment of the invention, FIG. 3 is a diagram for explaining the principle of operation, and FIG. 4 is an equivalent circuit diagram thereof. 8, 9, 10: Direction of electric field, 21: Semiconductor substrate, 22, 23: Slot line, 24: Coplanar line, 25: Center conductor of coplanar line, 2
6: Strip conductor, 35: Connection piece made of strip conductor on insulating layer, 36: Insulating layer, 37,3
8, 39: Input/output port.
Claims (1)
ロツト線路が形成され、上記半導体基板上にコプ
レナー線路が形成され、そのコプレナー線路の中
心導体は上記第１導体層に接続され、上記コプレ
ナー線路の外側２導体は上記第２導体層に接続さ
れ、上記中心導体と上記第１導体層との連結部と
上記第２導体層との間に絶縁層が介在されている
共平面回路。1. A slot line is formed on the semiconductor substrate by first and second conductor layers, a coplanar line is formed on the semiconductor substrate, the center conductor of the coplanar line is connected to the first conductor layer, and the center conductor of the coplanar line is connected to the first conductor layer. A coplanar circuit in which two outer conductors are connected to the second conductor layer, and an insulating layer is interposed between the connection portion between the center conductor and the first conductor layer and the second conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59010498A JPS60153603A (en) | 1984-01-23 | 1984-01-23 | Coplanar circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59010498A JPS60153603A (en) | 1984-01-23 | 1984-01-23 | Coplanar circuit |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19571688A Division JPH01117402A (en) | 1988-08-05 | 1988-08-05 | Coplanar circuit |
| JP19571588A Division JPH01117401A (en) | 1988-08-05 | 1988-08-05 | Coplanar circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60153603A JPS60153603A (en) | 1985-08-13 |
| JPS644361B2 true JPS644361B2 (en) | 1989-01-25 |
Family
ID=11751854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59010498A Granted JPS60153603A (en) | 1984-01-23 | 1984-01-23 | Coplanar circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60153603A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4739519A (en) * | 1985-10-31 | 1988-04-19 | Narda Western Operations | Coplanar microwave balun, multiplexer and mixer assemblies |
| JPH0770892B2 (en) * | 1986-01-20 | 1995-07-31 | 日本電信電話株式会社 | Coplanar hybrid circuit |
| JPH01177201A (en) * | 1988-01-06 | 1989-07-13 | A T R Koudenpa Tsushin Kenkyusho:Kk | Passive circuit device for microwave integrated circuit |
| JPH01117402A (en) * | 1988-08-05 | 1989-05-10 | Nippon Telegr & Teleph Corp <Ntt> | Coplanar circuit |
| US6265937B1 (en) | 1994-09-26 | 2001-07-24 | Endgate Corporation | Push-pull amplifier with dual coplanar transmission line |
| KR20200143363A (en) * | 2018-04-13 | 2020-12-23 | 에이지씨 가부시키가이샤 | Slot array antenna |
-
1984
- 1984-01-23 JP JP59010498A patent/JPS60153603A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60153603A (en) | 1985-08-13 |
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