JPS6441576A - Clamping circuit - Google Patents
Clamping circuitInfo
- Publication number
- JPS6441576A JPS6441576A JP62197742A JP19774287A JPS6441576A JP S6441576 A JPS6441576 A JP S6441576A JP 62197742 A JP62197742 A JP 62197742A JP 19774287 A JP19774287 A JP 19774287A JP S6441576 A JPS6441576 A JP S6441576A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- correction
- level
- sag
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Picture Signal Circuits (AREA)
Abstract
PURPOSE:To prevent a sharp change accompanied with a correction from being given to a television signal by executing the correction of a sag as to a digital television signal obtained by an A-D conversion and executing the staged correction in one horizontal scanning period. CONSTITUTION:An analog television signal is A-D-converted by an A-D converting circuit 3, and a difference from a clamping level (reference level) is calculated by a first subtracter circuit 5. The difference between an output (c) of a register 6 which is a sag component and an output (f) of an integration circuit 10 is calculated by a second subtracter circuit 7 and sent to a comparator circuit 8. At the comparator circuit 8, when a correction remainder exists, a level generating circuit 9 is controlled in order to generate a level to correct further. In such a way, when a correcting value is gradually outputted and the correct correcting value s outputted by the integration circuit 10, the output of the second subtracter circuit 7 goes to zero, the level is not added to the integration circuit 10 thereafter, and the correction of the sag is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62197742A JPS6441576A (en) | 1987-08-07 | 1987-08-07 | Clamping circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62197742A JPS6441576A (en) | 1987-08-07 | 1987-08-07 | Clamping circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6441576A true JPS6441576A (en) | 1989-02-13 |
Family
ID=16379587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62197742A Pending JPS6441576A (en) | 1987-08-07 | 1987-08-07 | Clamping circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6441576A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0651565A1 (en) * | 1993-11-02 | 1995-05-03 | Nec Corporation | Circuit for compensating the drift of the level of the direct current of a video signal |
-
1987
- 1987-08-07 JP JP62197742A patent/JPS6441576A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0651565A1 (en) * | 1993-11-02 | 1995-05-03 | Nec Corporation | Circuit for compensating the drift of the level of the direct current of a video signal |
| US5508749A (en) * | 1993-11-02 | 1996-04-16 | Nec Corporation | Sag compensation circuit for a video signal |
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