JPS6439114A - Pulse producing circuit - Google Patents

Pulse producing circuit

Info

Publication number
JPS6439114A
JPS6439114A JP19598487A JP19598487A JPS6439114A JP S6439114 A JPS6439114 A JP S6439114A JP 19598487 A JP19598487 A JP 19598487A JP 19598487 A JP19598487 A JP 19598487A JP S6439114 A JPS6439114 A JP S6439114A
Authority
JP
Japan
Prior art keywords
waveform
differential
supplied
pulse
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19598487A
Other languages
Japanese (ja)
Inventor
Hiroshi Muto
Takashi Aikawa
Takao Sugawara
Shinya Kawaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19598487A priority Critical patent/JPS6439114A/en
Publication of JPS6439114A publication Critical patent/JPS6439114A/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To produce pulses without applying bias voltage to a differential waveform and to avoid deterioration of the level margin, by adding a monostable multivibration circuit and two D .FFs to an absolute value differential pulse producing circuit. CONSTITUTION:The comparison 3 is carried out between differential waveforms C and D so that a waveform F is obtained. This waveform F is supplied to a monostable multivibration circuit 4. Thus the waveforms G and H are obtained with the positive and negative polarity outputs respectively. The waveform H is divided into two parts by a 1st D.FF 5 and a waveform I is obtained. The waveform I is supplied to a data terminal (d) of a 2nd D.FF 6 and the waveform G is supplied to a clock terminal (ck). The state of the terminal (d) is checked are the rise of the waveform G so that a waveform like a waveform J where the pulse rises only at the peak point of a reproduction signal is obtained at the output Q of the FF 6. Then the value of the pulse width TW is set smaller than the time Td, i.e., the positive or negative polarity of a differential, waveform and larger than the narrow pulse width. Thus it is possible to prevent the level margin deterioration due to the bias voltage of a pulse signal J.
JP19598487A 1987-08-04 1987-08-04 Pulse producing circuit Pending JPS6439114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19598487A JPS6439114A (en) 1987-08-04 1987-08-04 Pulse producing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19598487A JPS6439114A (en) 1987-08-04 1987-08-04 Pulse producing circuit

Publications (1)

Publication Number Publication Date
JPS6439114A true JPS6439114A (en) 1989-02-09

Family

ID=16350277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19598487A Pending JPS6439114A (en) 1987-08-04 1987-08-04 Pulse producing circuit

Country Status (1)

Country Link
JP (1) JPS6439114A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04291509A (en) * 1991-03-20 1992-10-15 Nec Corp Dc compensation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04291509A (en) * 1991-03-20 1992-10-15 Nec Corp Dc compensation circuit

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