JPS6437649A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS6437649A
JPS6437649A JP19368887A JP19368887A JPS6437649A JP S6437649 A JPS6437649 A JP S6437649A JP 19368887 A JP19368887 A JP 19368887A JP 19368887 A JP19368887 A JP 19368887A JP S6437649 A JPS6437649 A JP S6437649A
Authority
JP
Japan
Prior art keywords
processor
biu1
mpu1
cpu
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19368887A
Other languages
Japanese (ja)
Other versions
JPH0682348B2 (en
Inventor
Etsuro Odan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19368887A priority Critical patent/JPH0682348B2/en
Publication of JPS6437649A publication Critical patent/JPS6437649A/en
Publication of JPH0682348B2 publication Critical patent/JPH0682348B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To make processing efficient by constituting the titled system so that interruption processing based upon an I/O processor is not executed at the time of generating a status input instruction. CONSTITUTION:A central processing unit (CPU) 101 has an arithmetic processor 103 and a bus control unit (BIU0) 104 is connected to a bus 110 through the BIU0 104. On the other hand, an I/O processor (IOP) 102 has an I/O processor (MPU1) 106, a bus control unit (BIU1) 105 and a local memory (LM) 107 and is connected to the bus 110 through the BIU1 105 and connected to an I/O device 108 through the MPU1 106. When the CPU 101 executes a status input instruction to the IOP 102, the BIU1 105 reads out status information stored in a previously determined address in the LM 107 without generating an interruption to the MPU1 106 and transfers the concerned status information to the CPU 101.
JP19368887A 1987-08-04 1987-08-04 I / O control method Expired - Lifetime JPH0682348B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19368887A JPH0682348B2 (en) 1987-08-04 1987-08-04 I / O control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19368887A JPH0682348B2 (en) 1987-08-04 1987-08-04 I / O control method

Publications (2)

Publication Number Publication Date
JPS6437649A true JPS6437649A (en) 1989-02-08
JPH0682348B2 JPH0682348B2 (en) 1994-10-19

Family

ID=16312127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19368887A Expired - Lifetime JPH0682348B2 (en) 1987-08-04 1987-08-04 I / O control method

Country Status (1)

Country Link
JP (1) JPH0682348B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0441928U (en) * 1990-07-20 1992-04-09

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0441928U (en) * 1990-07-20 1992-04-09

Also Published As

Publication number Publication date
JPH0682348B2 (en) 1994-10-19

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