JPS6414655A - Data transfer device - Google Patents

Data transfer device

Info

Publication number
JPS6414655A
JPS6414655A JP16878487A JP16878487A JPS6414655A JP S6414655 A JPS6414655 A JP S6414655A JP 16878487 A JP16878487 A JP 16878487A JP 16878487 A JP16878487 A JP 16878487A JP S6414655 A JPS6414655 A JP S6414655A
Authority
JP
Japan
Prior art keywords
instruction
control circuit
dma control
processor
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16878487A
Other languages
Japanese (ja)
Inventor
Fumio Usui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16878487A priority Critical patent/JPS6414655A/en
Publication of JPS6414655A publication Critical patent/JPS6414655A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To efficiently operate a DMA control circuit without deteriorating the processing efficiency of a processor, by providing an instruction table store exclusive memory on a local bus of the DMA control circuit, which can be separated from a shred bus of the processor and the DMA control circuit, storing an instruction table and reading out an instruction through the local bus therefrom. CONSTITUTION:When an instruction decoding circuit 3 of a DMA control circuit 2 reads out an instruction from an instruction table 8, the DMA control circuit 2 and the instruction table 8 are detached from a shared bus 9, and they are connected directly by local buses 10, 11. Accordingly, while the instruction decoding circuit 3 of the DMA control circuit 2 is reading out an instruction from the instruction table 8, a processor 1 can use the shared bus 9, and during this time, the processor can execute the processing by using the shared bus.
JP16878487A 1987-07-08 1987-07-08 Data transfer device Pending JPS6414655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16878487A JPS6414655A (en) 1987-07-08 1987-07-08 Data transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16878487A JPS6414655A (en) 1987-07-08 1987-07-08 Data transfer device

Publications (1)

Publication Number Publication Date
JPS6414655A true JPS6414655A (en) 1989-01-18

Family

ID=15874406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16878487A Pending JPS6414655A (en) 1987-07-08 1987-07-08 Data transfer device

Country Status (1)

Country Link
JP (1) JPS6414655A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU774018B2 (en) * 2000-01-07 2004-06-10 Phild Co., Ltd. Hair styling method
CN1322441C (en) * 2003-10-30 2007-06-20 株式会社东芝 Multi-chip package type memory system
EP2393013A3 (en) * 2010-06-03 2012-09-05 Designart Networks Ltd Method and apparatus for wireless broadband systems direct data transfer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU774018B2 (en) * 2000-01-07 2004-06-10 Phild Co., Ltd. Hair styling method
CN1322441C (en) * 2003-10-30 2007-06-20 株式会社东芝 Multi-chip package type memory system
EP2393013A3 (en) * 2010-06-03 2012-09-05 Designart Networks Ltd Method and apparatus for wireless broadband systems direct data transfer

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