JPS6436281A - Action detecting circuit - Google Patents

Action detecting circuit

Info

Publication number
JPS6436281A
JPS6436281A JP62191933A JP19193387A JPS6436281A JP S6436281 A JPS6436281 A JP S6436281A JP 62191933 A JP62191933 A JP 62191933A JP 19193387 A JP19193387 A JP 19193387A JP S6436281 A JPS6436281 A JP S6436281A
Authority
JP
Japan
Prior art keywords
pair
action detecting
signal
supplied
frame difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62191933A
Other languages
Japanese (ja)
Inventor
Ryoichi Kurihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62191933A priority Critical patent/JPS6436281A/en
Publication of JPS6436281A publication Critical patent/JPS6436281A/en
Pending legal-status Critical Current

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  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

PURPOSE:To approximate to a frame difference signal and to obtain an action detecting signal being removed a noise component by forming two comparing outputs with a pair of reference levels different in threshold level, and using a pair of comparing outputs and a delaying output. CONSTITUTION:The reference level of a first comparator 11 is set to a prescribed threshold level SH in the same manner as the conventional one. In the same way, the reference level of a second comparator 12 is set to a prescribed threshold level SL lower than SH. A frame difference signal S supplied to a terminal 1 is supplied to a pair of these comparators 11 and 12 and thus, a pair of comparing outputs (a) and (b) is outputted. For a second comparing output (b), only a prescribed time T0 is delayed in a delaying circuit 13. A pair of the comparing outputs (a) and (b) and a delaying output (f) are supplied to a hysteresis circuit 20. A final action detecting signal (i) is obtained from the circuit 20. The action detecting signal (i) has a pulse width W to meet approximately the current frame difference signal S and is obtained as a signal in which a noise component N is removed.
JP62191933A 1987-07-31 1987-07-31 Action detecting circuit Pending JPS6436281A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62191933A JPS6436281A (en) 1987-07-31 1987-07-31 Action detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62191933A JPS6436281A (en) 1987-07-31 1987-07-31 Action detecting circuit

Publications (1)

Publication Number Publication Date
JPS6436281A true JPS6436281A (en) 1989-02-07

Family

ID=16282863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62191933A Pending JPS6436281A (en) 1987-07-31 1987-07-31 Action detecting circuit

Country Status (1)

Country Link
JP (1) JPS6436281A (en)

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