JPS6434133A - Input protective circuit - Google Patents
Input protective circuitInfo
- Publication number
- JPS6434133A JPS6434133A JP18936387A JP18936387A JPS6434133A JP S6434133 A JPS6434133 A JP S6434133A JP 18936387 A JP18936387 A JP 18936387A JP 18936387 A JP18936387 A JP 18936387A JP S6434133 A JPS6434133 A JP S6434133A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- semiconductor element
- protective circuit
- package
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Emergency Protection Circuit Devices (AREA)
Abstract
PURPOSE:To enhance the surge breakdown resistance of a semiconductor element even if an external resistor is not used by connecting a lead frame to a chip by a semiconductor element sealed in a package through a resistor. CONSTITUTION:When a semiconductor element sealed in a package 12 is formed, a chip 10 is electrically connected to a lead frame 9 through a resistor. This resistor may be formed of a bonding wiring 11 itself, or another resistor may be interposed between the wire 11 and the frame 9. Thus, even if an external resistor is not provided at the input terminal of the element, the surge breakdown resistance of the element can be enhanced. Further, the mounting efficiency of a printed wiring board can be raised.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18936387A JPS6434133A (en) | 1987-07-28 | 1987-07-28 | Input protective circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18936387A JPS6434133A (en) | 1987-07-28 | 1987-07-28 | Input protective circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6434133A true JPS6434133A (en) | 1989-02-03 |
Family
ID=16240068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18936387A Pending JPS6434133A (en) | 1987-07-28 | 1987-07-28 | Input protective circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6434133A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003031710A (en) * | 2001-07-12 | 2003-01-31 | Mitsumi Electric Co Ltd | Monolithic ic package |
JPWO2006059381A1 (en) * | 2004-12-01 | 2008-08-07 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method of semiconductor device |
-
1987
- 1987-07-28 JP JP18936387A patent/JPS6434133A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003031710A (en) * | 2001-07-12 | 2003-01-31 | Mitsumi Electric Co Ltd | Monolithic ic package |
JPWO2006059381A1 (en) * | 2004-12-01 | 2008-08-07 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method of semiconductor device |
JP4574624B2 (en) * | 2004-12-01 | 2010-11-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
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