JPS6432359A - Memory device - Google Patents

Memory device

Info

Publication number
JPS6432359A
JPS6432359A JP62189618A JP18961887A JPS6432359A JP S6432359 A JPS6432359 A JP S6432359A JP 62189618 A JP62189618 A JP 62189618A JP 18961887 A JP18961887 A JP 18961887A JP S6432359 A JPS6432359 A JP S6432359A
Authority
JP
Japan
Prior art keywords
parity
memory
address
written
write address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62189618A
Other languages
Japanese (ja)
Inventor
Atsushi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62189618A priority Critical patent/JPS6432359A/en
Publication of JPS6432359A publication Critical patent/JPS6432359A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To specify an address where the data is written by mistake by writing the parity of the corresponding data into a memory chip after inverting it when a write address error is detected by a parity check. CONSTITUTION:A write address is supplied from a CPU 2 via a memory address register 11 and a parity error detecting circuit 12 decides the parity of the write address. When an error of the write address is detected, the output of the circuit 12 is inverted into 1. Thus an AND gate 17 is opened and the parity 15 of the corresponding data received from a data register 15 is turned into an inverted parity showing the data destructed intentionally. This inverted parity is written into a memory 21 via a NOT gate 16. In the same way, the parity 15 is written as it is into the memory 21 when the write address has no error. Therefore it is possible to surely grasp and address where the wrong data is written by reading and scanning the memory 21.
JP62189618A 1987-07-29 1987-07-29 Memory device Pending JPS6432359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62189618A JPS6432359A (en) 1987-07-29 1987-07-29 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62189618A JPS6432359A (en) 1987-07-29 1987-07-29 Memory device

Publications (1)

Publication Number Publication Date
JPS6432359A true JPS6432359A (en) 1989-02-02

Family

ID=16244315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62189618A Pending JPS6432359A (en) 1987-07-29 1987-07-29 Memory device

Country Status (1)

Country Link
JP (1) JPS6432359A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08286977A (en) * 1995-04-14 1996-11-01 Kofu Nippon Denki Kk System for processing fault of in-store cache
JP2002268354A (en) * 2001-03-09 2002-09-18 Ricoh Co Ltd Toner-replenishing device
WO2003068468A1 (en) 2002-02-14 2003-08-21 Norsk Hydro Asa A method and equipment for compacting materials

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08286977A (en) * 1995-04-14 1996-11-01 Kofu Nippon Denki Kk System for processing fault of in-store cache
JP2002268354A (en) * 2001-03-09 2002-09-18 Ricoh Co Ltd Toner-replenishing device
WO2003068468A1 (en) 2002-02-14 2003-08-21 Norsk Hydro Asa A method and equipment for compacting materials

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