JPS6432306A - Display system for pmc cycle time - Google Patents

Display system for pmc cycle time

Info

Publication number
JPS6432306A
JPS6432306A JP62189614A JP18961487A JPS6432306A JP S6432306 A JPS6432306 A JP S6432306A JP 62189614 A JP62189614 A JP 62189614A JP 18961487 A JP18961487 A JP 18961487A JP S6432306 A JPS6432306 A JP S6432306A
Authority
JP
Japan
Prior art keywords
time
minimum
value
cycle
maximum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62189614A
Other languages
Japanese (ja)
Inventor
Yoshiaki Ikeda
Masuo Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP62189614A priority Critical patent/JPS6432306A/en
Publication of JPS6432306A publication Critical patent/JPS6432306A/en
Pending legal-status Critical Current

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  • Testing And Monitoring For Control Systems (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To accurately grasp both maximum and minimum cycle times by actually executing a sequence program to replace said cycle times and displaying these replaced values. CONSTITUTION:The time Tn is read out of a timer and at the same time the previous time T0 is read out of a memory 30 for calculation of the actual cycle time Tc=Tn-T0. When the measure cycle time Tc is larger than the maximum value Tmax of the stored cycle time, the time Tc is substituted for the value Tmax for acquisition of the maximum value. When the time Tc is smaller than the value Tmax, the time Tc is composed with the stored minimum time Tmin. If the time Tc is smaller than the value Tmin, the time Tc is replaced with the value Tmin for acuisition of the minimum time. Then the memory time T0 is replaced with the time Tn. Both maximum and minimum values are displayed on a display device 43.
JP62189614A 1987-07-29 1987-07-29 Display system for pmc cycle time Pending JPS6432306A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62189614A JPS6432306A (en) 1987-07-29 1987-07-29 Display system for pmc cycle time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62189614A JPS6432306A (en) 1987-07-29 1987-07-29 Display system for pmc cycle time

Publications (1)

Publication Number Publication Date
JPS6432306A true JPS6432306A (en) 1989-02-02

Family

ID=16244251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62189614A Pending JPS6432306A (en) 1987-07-29 1987-07-29 Display system for pmc cycle time

Country Status (1)

Country Link
JP (1) JPS6432306A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144840A (en) * 1984-01-05 1985-07-31 Fuji Electric Co Ltd Measurement system for program cycle
JPS6215606A (en) * 1985-07-15 1987-01-24 Fuji Electric Co Ltd Method for confirming executing speed of programmable controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144840A (en) * 1984-01-05 1985-07-31 Fuji Electric Co Ltd Measurement system for program cycle
JPS6215606A (en) * 1985-07-15 1987-01-24 Fuji Electric Co Ltd Method for confirming executing speed of programmable controller

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