JPS6430258A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS6430258A
JPS6430258A JP62186840A JP18684087A JPS6430258A JP S6430258 A JPS6430258 A JP S6430258A JP 62186840 A JP62186840 A JP 62186840A JP 18684087 A JP18684087 A JP 18684087A JP S6430258 A JPS6430258 A JP S6430258A
Authority
JP
Japan
Prior art keywords
bit
capacitor
wire
mosfets
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62186840A
Other languages
Japanese (ja)
Inventor
Norimasa Matsumoto
Kazutami Arimoto
Koichiro Masuko
Kiyohiro Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62186840A priority Critical patent/JPS6430258A/en
Publication of JPS6430258A publication Critical patent/JPS6430258A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To simplify a memory cell structure and an enviromental circuit as well by a method wherein two bit wires, a bit wire and an inverting bit wire, are provided, a capacitor is provided between the bit wires through intermediary of two MOSFETs as transfer gates, and two MOSFETs are made to consist of a three-layered structure. CONSTITUTION:A bit wire BL is connected with a source of a MOSFET (TR1a) and an inverting bit wire -BL is connected with a source of a TR1b. When a word wire WL is selected to be at a high level, the MOSFETs, (TR1a) and (TR1b) are made to be conductive, and write-in and read-out of the information from an information charge storing capacitor C1 are executed. Here, when alpharays hit the capacitor C1, the potential decreases as electrons are injected into an n+ diffusion layer 4, but a first polycrystalline Si layer 6 is made to decrease in potential owing to the capacitor coupling, which effect is read out between the bit wires BL and -BL, and thus the sensed information is not inverted.
JP62186840A 1987-07-27 1987-07-27 Semiconductor storage device Pending JPS6430258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62186840A JPS6430258A (en) 1987-07-27 1987-07-27 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62186840A JPS6430258A (en) 1987-07-27 1987-07-27 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6430258A true JPS6430258A (en) 1989-02-01

Family

ID=16195551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62186840A Pending JPS6430258A (en) 1987-07-27 1987-07-27 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6430258A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328743B1 (en) * 1995-11-28 2002-10-31 삼성전자 주식회사 Ferroelectric dynamic random access memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328743B1 (en) * 1995-11-28 2002-10-31 삼성전자 주식회사 Ferroelectric dynamic random access memory

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