JPS6424834U - - Google Patents
Info
- Publication number
- JPS6424834U JPS6424834U JP11964087U JP11964087U JPS6424834U JP S6424834 U JPS6424834 U JP S6424834U JP 11964087 U JP11964087 U JP 11964087U JP 11964087 U JP11964087 U JP 11964087U JP S6424834 U JPS6424834 U JP S6424834U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- stand
- grooves
- substrate
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Die Bonding (AREA)
Description
第１図は本考案の一実施例に係るチツプ台と基
板との接着要領を示す斜視図で、第２図は第１図
における矢視Ａ―Ａ線に沿つて切断した断面図で
ある。
１……チツプ台、２……凹溝、３……半導体チ
ツプ、４……ダイボンド剤、５……接着剤、６…
…基板、７……窓。
FIG. 1 is a perspective view showing a procedure for bonding a chip base and a substrate according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line A--A in FIG. 1. DESCRIPTION OF SYMBOLS 1... Chip stand, 2... Concave groove, 3... Semiconductor chip, 4... Die bonding agent, 5... Adhesive, 6...
...board, 7...window.
Claims (1)
面に、多数の凹溝を形成せしめたことを特徴とす
るチツプ台。 A chip stand is characterized in that a large number of grooves are formed on the surface of the chip stand of a semiconductor chip bonded to a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11964087U JPS6424834U (en) | 1987-08-04 | 1987-08-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11964087U JPS6424834U (en) | 1987-08-04 | 1987-08-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6424834U true JPS6424834U (en) | 1989-02-10 |
Family
ID=31365042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11964087U Pending JPS6424834U (en) | 1987-08-04 | 1987-08-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6424834U (en) |
-
1987
- 1987-08-04 JP JP11964087U patent/JPS6424834U/ja active Pending