JPS63200338U - - Google Patents
Info
- Publication number
- JPS63200338U JPS63200338U JP9105287U JP9105287U JPS63200338U JP S63200338 U JPS63200338 U JP S63200338U JP 9105287 U JP9105287 U JP 9105287U JP 9105287 U JP9105287 U JP 9105287U JP S63200338 U JPS63200338 U JP S63200338U
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- base
- die bonding
- semiconductor chip
- place
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図乃至第４図は本考案の実施例であり、第
５図は従来例である。第１図は平面図、第２図は
第１図の―線断面図、第３図乃至第５図はダ
イボンデイング工程を示す断面図である。
符号の説明、１…ヒートシンク、２…台部、３
…一般面、４…半導体チツプ、５…ハンダ、６…
余剰ハンダ。
1 to 4 show examples of the present invention, and FIG. 5 shows a conventional example. FIG. 1 is a plan view, FIG. 2 is a sectional view taken along the line -- in FIG. 1, and FIGS. 3 to 5 are sectional views showing the die bonding process. Explanation of symbols, 1...Heat sink, 2...Base, 3
...General surface, 4...Semiconductor chip, 5...Solder, 6...
Surplus solder.
Claims (1)
ートシンクにおいて、一般面より上方へ突出し、
かつ、前記半導体チツプを載置可能な大きさの頂
面を有する台部を形成したことを特徴とするヒー
トシンク。 In a heat sink for die bonding semiconductor chips, the heat sink protrudes above the general surface,
A heat sink further comprising a base having a top surface large enough to place the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9105287U JPS63200338U (en) | 1987-06-13 | 1987-06-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9105287U JPS63200338U (en) | 1987-06-13 | 1987-06-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63200338U true JPS63200338U (en) | 1988-12-23 |
Family
ID=30951480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9105287U Pending JPS63200338U (en) | 1987-06-13 | 1987-06-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63200338U (en) |
-
1987
- 1987-06-13 JP JP9105287U patent/JPS63200338U/ja active Pending