JPS6423304A - Circuit control system for cell controller - Google Patents

Circuit control system for cell controller

Info

Publication number
JPS6423304A
JPS6423304A JP17912287A JP17912287A JPS6423304A JP S6423304 A JPS6423304 A JP S6423304A JP 17912287 A JP17912287 A JP 17912287A JP 17912287 A JP17912287 A JP 17912287A JP S6423304 A JPS6423304 A JP S6423304A
Authority
JP
Japan
Prior art keywords
adaptors
controller
controllers
cell
circuit control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17912287A
Other languages
Japanese (ja)
Inventor
Yukio Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP17912287A priority Critical patent/JPS6423304A/en
Publication of JPS6423304A publication Critical patent/JPS6423304A/en
Pending legal-status Critical Current

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  • Numerical Control (AREA)

Abstract

PURPOSE:To reduce the load of a microprocessor by connecting two numerical controllers to a communication adaptor of a cell-controller and outputted the NC data alternately from buffers of a shared memory via said communication adaptor so that those numerical controllers are controlled by the cell-controller. CONSTITUTION:The communication adaptors 17 and 18 are added to a circuit control type cell-controller 10 and four numerical controllers NC1-4 are con nected to both adaptors 17 and 18 via circuits CH1-4 respectively. The NC request signals received from controllers NC1-4 are sent to a main microprocessor MPU 11 via adaptors 17 and 18. The NC data stored in each buffer of a shared RAM 14 are read out alternately to adaptors 17 and 18 based on the program of a ROM 12. Then the adaptors 17 and 18 supply these NC data to controllers NC1-4 respectively. The cell-controller 10 controls the circuits CH1-4. Thus the load of the MPU 11 is reduced.
JP17912287A 1987-07-20 1987-07-20 Circuit control system for cell controller Pending JPS6423304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17912287A JPS6423304A (en) 1987-07-20 1987-07-20 Circuit control system for cell controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17912287A JPS6423304A (en) 1987-07-20 1987-07-20 Circuit control system for cell controller

Publications (1)

Publication Number Publication Date
JPS6423304A true JPS6423304A (en) 1989-01-26

Family

ID=16060385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17912287A Pending JPS6423304A (en) 1987-07-20 1987-07-20 Circuit control system for cell controller

Country Status (1)

Country Link
JP (1) JPS6423304A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993004416A1 (en) * 1991-08-16 1993-03-04 Hitachi Seiko, Ltd. Cnc system for controlling a plurality of machines

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993004416A1 (en) * 1991-08-16 1993-03-04 Hitachi Seiko, Ltd. Cnc system for controlling a plurality of machines

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