JPS5762414A - Programmable controller - Google Patents
Programmable controllerInfo
- Publication number
- JPS5762414A JPS5762414A JP13807680A JP13807680A JPS5762414A JP S5762414 A JPS5762414 A JP S5762414A JP 13807680 A JP13807680 A JP 13807680A JP 13807680 A JP13807680 A JP 13807680A JP S5762414 A JPS5762414 A JP S5762414A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- address
- address signal
- ram3
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/056—Programming the PLC
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Programmable Controllers (AREA)
Abstract
PURPOSE:To reduce a load on a CPU by performing data trasfer between an input and output RAM and an input and output unit group and a series of control operations accompanying the transfer in a shorter procesing time without the intervention of the CPU. CONSTITUTION:Through an address bus AB2 connecting wit an input and output unit group 1 and disconnected from an address bus AB1, a scanning address signal generated by an address counter 6 is transmitted. A selecting circuit 7 controlled by a CPU2 selects either one of and address signal trnsmitted through the address bus AB1 of the CPU2 side and the scanning address signal generated by the address counter 6, thereby obtaining the address signal of an input and output RAM3. Further, input-output discrimination signals transmitted from input or output units 1a and 1b selected by the said scanning address signal are supplied directly to the input and output RAM3 through a signal line l1. Consequently, the operation mode of the input and output RAM3 is controlled from the input and output unit group 1 in addititon to the CPU2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13807680A JPS5762414A (en) | 1980-10-02 | 1980-10-02 | Programmable controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13807680A JPS5762414A (en) | 1980-10-02 | 1980-10-02 | Programmable controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5762414A true JPS5762414A (en) | 1982-04-15 |
Family
ID=15213394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13807680A Pending JPS5762414A (en) | 1980-10-02 | 1980-10-02 | Programmable controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5762414A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59174604U (en) * | 1983-05-11 | 1984-11-21 | 富士電機株式会社 | AC output drive device for sequence controller |
JPS60251406A (en) * | 1984-05-28 | 1985-12-12 | Omron Tateisi Electronics Co | Programmable controller |
-
1980
- 1980-10-02 JP JP13807680A patent/JPS5762414A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59174604U (en) * | 1983-05-11 | 1984-11-21 | 富士電機株式会社 | AC output drive device for sequence controller |
JPS60251406A (en) * | 1984-05-28 | 1985-12-12 | Omron Tateisi Electronics Co | Programmable controller |
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