JPS6423114U - - Google Patents

Info

Publication number
JPS6423114U
JPS6423114U JP11706887U JP11706887U JPS6423114U JP S6423114 U JPS6423114 U JP S6423114U JP 11706887 U JP11706887 U JP 11706887U JP 11706887 U JP11706887 U JP 11706887U JP S6423114 U JPS6423114 U JP S6423114U
Authority
JP
Japan
Prior art keywords
oscillator
signals
output signals
integrator
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11706887U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11706887U priority Critical patent/JPS6423114U/ja
Publication of JPS6423114U publication Critical patent/JPS6423114U/ja
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示すブロツク回路図
、第2図は高周波リンクインバータのブロツク回
路図、第3図は第2図のインバータ装置の各部の
電圧波形図である。 2……高周波発振器、2……低周波発振器
、3,3……乗算器、4,4……積分器
、5……加算器。
FIG. 1 is a block circuit diagram showing an embodiment of the present invention, FIG. 2 is a block circuit diagram of a high frequency link inverter, and FIG. 3 is a voltage waveform diagram of various parts of the inverter device of FIG. 2. 2 1 ... high frequency oscillator, 2 2 ... low frequency oscillator, 3 1 , 3 2 ... multiplier, 4 1 , 4 2 ... integrator, 5 ... adder.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 互いに異なる周波数の正弦波信号を出力する第
1の発振器及び第2の発振器と、これらの発振器
の出力信号を互いに乗算する第1の乗算器と、前
記第1の発振器及び第2の発振器の出力信号を夫
々積分する第1の積分器及び第2の積分器と、こ
れらの積分器の出力信号を互いに乗算する第2の
乗算器と、前記第1の乗算器及び第2の乗算器の
各出力信号を互いに加算する加算器とを有してな
ることを特徴とする差周波発振器。
a first oscillator and a second oscillator that output sinusoidal signals of different frequencies; a first multiplier that multiplies the output signals of these oscillators; and outputs of the first oscillator and the second oscillator. a first integrator and a second integrator that respectively integrate signals; a second multiplier that multiplies the output signals of these integrators; and each of the first and second multipliers. A difference frequency oscillator comprising: an adder that adds output signals to each other.
JP11706887U 1987-07-30 1987-07-30 Pending JPS6423114U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11706887U JPS6423114U (en) 1987-07-30 1987-07-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11706887U JPS6423114U (en) 1987-07-30 1987-07-30

Publications (1)

Publication Number Publication Date
JPS6423114U true JPS6423114U (en) 1989-02-07

Family

ID=31360183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11706887U Pending JPS6423114U (en) 1987-07-30 1987-07-30

Country Status (1)

Country Link
JP (1) JPS6423114U (en)

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